Part Number: ADC12J4000EVM Other Parts Discussed in Thread: ADC12J4000 Hello,
Our original FPGA(Xilinx KU060) board is combined ADC12J4000EVM via FMC.
I'm checking the received data from ADC12J4000(JESD204B) using ChipScope on FPGA.
It seems the Ramp_Test_Data…
Part Number: ADC12J4000 Other Parts Discussed in Thread: LMK04828 , TRF3765 , Hi
The clock circuit of development board ADC12J4000 includes TRF3765 and LMK04828. It is found that the clock given to FPGA is contrary to the polarity of the clock（DEVCLKARX_P…
Part Number: ADC12J4000 Hello
We use an ADC12J4000 with a periodic SYSREF (about 2.56??Mhz) strictly synchronous with DEVCLK (about 4Ghz) through using a device similar LMK048??.
The periodic SYSREF is a clock with 50% duty-cycle. We can't change the…
Hi Avantx
As long as the following criteria are met the phase alignment of captured input signals should be consistent:
All ADCs have consistent NCO frequency/phase settings
SYSREF is properly captured at each ADC and the FPGA on a consistent CLK ed…
Part Number: ADC12J4000 Other Parts Discussed in Thread: ADC12DJ3200 Hello again!
During last experiments with adc12j4000, we encountered unexpected behavior of device.
ADC produces significant spur at Fs/4. It happens in different modes (bypass, dec…
Part Number: ADC12J4000 Hi,
Customer is using ADC12J4000EVM, then I have a question about ADC Test Pattern. The ADC sent the ADC Test Pattern, however, the FPGA received the different data as follows. Please let me know the root cause of this issue.
…
Hi Itai
The answer may depend on the frequency of your input signal.
If the reduced slew rate results in higher jitter at the ADC clock inputs it could impact the SNR of the converted waveform at higher input frequencies.
Best regards,
Jim B
Part Number: ADC12J4000 Other Parts Discussed in Thread: LMX2594 , , ADC12DJ3200 Hi,
I am trying to link ADC12J4000 to xilinx xc7vx690t by xilinx jesd204b ip core on my board, we are using lmx2594 so the sampling clock could up to 4GHz, we are going to…
Part Number: ADC12J4000 What is the definition of the differential full scale input range for the ADC12J4000? The data sheet shows that the full scale range can be set between 500mV and 950mVpp (7.3.5.4), it is not clear if this is 500-950mVpp after a…
