Part Number: ADC12J4000 Other Parts Discussed in Thread: 66AK2L06 , , Tool/software: Linux Hello
We currently try to use the ADC12J4000 boad in combination with the 66AK2L06 board.
So i want to control the ADC12J4000EVM GUI.
But i cannot setup the communication…
Part Number: ADC12J4000EVM Other Parts Discussed in Thread: ADC12J4000 Hello,
Our original FPGA(Xilinx KU060) board is combined ADC12J4000EVM via FMC.
I'm checking the received data from ADC12J4000(JESD204B) using ChipScope on FPGA.
It seems the Ramp_Test_Data…
Part Number: ADC12J4000 Hello
We use an ADC12J4000 with a periodic SYSREF (about 2.56??Mhz) strictly synchronous with DEVCLK (about 4Ghz) through using a device similar LMK048??.
The periodic SYSREF is a clock with 50% duty-cycle. We can't change the…
Part Number: ADC12J4000 Other Parts Discussed in Thread: LMK04828 , TRF3765 , Hi
The clock circuit of development board ADC12J4000 includes TRF3765 and LMK04828. It is found that the clock given to FPGA is contrary to the polarity of the clock（DEVCLKARX_P…
As long as the following criteria are met the phase alignment of captured input signals should be consistent:
All ADCs have consistent NCO frequency/phase settings
SYSREF is properly captured at each ADC and the FPGA on a consistent CLK ed…
The answer may depend on the frequency of your input signal.
If the reduced slew rate results in higher jitter at the ADC clock inputs it could impact the SNR of the converted waveform at higher input frequencies.
Part Number: ADC12J4000EVM Other Parts Discussed in Thread: ADC12J4000 , LMK04828 , , TSW14J10EVM , TRF3765 HELLO,
I AM USING ADC12J4000 BOARD AND INTERFACING IT WITH ZC706 BOARD.
I AM USING JESD204B IP AS A RECEIVER RUNNING IN 8,8,8 MODE. THESE ARE THE SET…