Part Number: ADC12QJ800 Tool/software: We have two ADCs receiving delay matched device clocks, then PLLs used to derive sampling clocks. Is there delay, or more importantly, temperature dependent, delay going through PLLs?
We are would like to know how…
Part Number: ADC12QJ800 Tool/software: I have low frequency device clock (85MHz) and using PLL to generate sampling clock.
SYSREF is generated in FPGA, and thus can easily meet a traditional setup and hold requirement at ADC.
Can the windowing be bypassed…
Part Number: ADC12QJ800 Hi team,
The sample rate is 500M and SYSREF is 781.25K from the clock chip. In normal mode, when no input is connected, all 0 data is captured, when 200mV input is added, the data becomes garbled. Does not correspond to the transfer…
Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 We are currently in the process of developing a new data acquisition system for one of our products using the ADC12QJ800 interfaced to the TI-JESD204 IP modified from the zcu102 reference…
Part Number: ADC12QJ800-Q1 Hi There,
The ADC has 800 MSPS so it must be for each channel (A, B, C, D). I mean sampling rate will not split between channels. Please confirm.
Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 Hi Team,
I'm u sing the ADC12QJ800 chip's JMODE0 mode to collect data. Could you tell me how to splice the data received by the FPGA receiving end to obtain the sampling data?…
Part Number: ADC12QJ800 We are interesed in integrating the TI JESD204B IP Core (TI204c IP core) into Xilinx Zynq UltraScale+ FPGA. The TI questionaire asks me which MODE I need.
What is this MODE and how do I find out which MODE I need?
Please advise…
