Part Number: ADC12QJ800 Other Parts Discussed in Thread: TI-JESD204-IP Tool/software: Hello,
We are trying to bring up the ADC12QJ800 on our custom development board with an XC7K325T-2FFG900 FPGA. We’re encountering an issue with the JESD interface…
Part Number: ADC12QJ800 Tool/software:
Hi,
We are using the tool to configure the part with:
83.968MHz differential input clock,
671.744MHz sampling clock,
JMODE 4,
11083.766Mbps serial lane rate.
TRIGOUT to be serial rate/64 = 173.184MHz…
Part Number: ADC12QJ800 Tool/software: We are ramp testing JESD on ADC12QJ800.
Output of JESD (withing FPGA using Vivado) looks like this:
Is this correct for half of the lanes to have different ramp period?
Part Number: ADC12QJ800 Tool/software: We have two ADCs receiving delay matched device clocks, then PLLs used to derive sampling clocks. Is there delay, or more importantly, temperature dependent, delay going through PLLs?
We are would like to know…
Part Number: ADC12QJ800 Tool/software: I have low frequency device clock (85MHz) and using PLL to generate sampling clock.
SYSREF is generated in FPGA, and thus can easily meet a traditional setup and hold requirement at ADC.
Can the windowing be…
Part Number: ADC12QJ800 Hi team,
The sample rate is 500M and SYSREF is 781.25K from the clock chip. In normal mode, when no input is connected, all 0 data is captured, when 200mV input is added, the data becomes garbled. Does not correspond to the transfer…
Part Number: ADC12QJ800-Q1 Hi There,
The ADC has 800 MSPS so it must be for each channel (A, B, C, D). I mean sampling rate will not split between channels. Please confirm.
Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 We are currently in the process of developing a new data acquisition system for one of our products using the ADC12QJ800 interfaced to the TI-JESD204 IP modified from the zcu102 reference…
Part Number: ADC12QJ800-Q1 Hi team,
One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions?
Requirements:
The device input clock uses a differential clock: Input 144MHz,
Use CPLL to generate…
