Hi Rob,
Thanks for your response.
I think that is the point. After rearranging this format, the real sample data is normal, and it should be that the coding order I understood was wrong.
Regards,
Amy
Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 We are currently in the process of developing a new data acquisition system for one of our products using the ADC12QJ800 interfaced to the TI-JESD204 IP modified from the zcu102 reference…
Part Number: ADC12QJ800-Q1 Hi There,
The ADC has 800 MSPS so it must be for each channel (A, B, C, D). I mean sampling rate will not split between channels. Please confirm.
Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 Hi Team,
I'm u sing the ADC12QJ800 chip's JMODE0 mode to collect data. Could you tell me how to splice the data received by the FPGA receiving end to obtain the sampling data?…
Part Number: ADC12QJ800 We are interesed in integrating the TI JESD204B IP Core (TI204c IP core) into Xilinx Zynq UltraScale+ FPGA. The TI questionaire asks me which MODE I need.
What is this MODE and how do I find out which MODE I need?
Please advise…
Felix,
For the ADC, take a look at the ADS54J66, ADS54J54, ADS58J63 or the ADC12QJ800.
For the DAC, take a look at the DAC3161 or DAC3171.
Regards,
Jim