Part Number: ADC3660EVM I have an ADC3660EVM board and two different schematics neither of which match the board.
How do I determine the revision number and find a schematic that matches?
Part Number: ADC3660EVM Hi,
I am using a linux utility "spidev_test" to write into ADC register. For example if I want to write a value of 0x6c at offset of 0x70 , I use the following command:- $ spidev_test -D /dev/spidev1.0 -s 1000000 -H -O…
Part Number: ADC3660EVM Other Parts Discussed in Thread: DATACONVERTERPRO-SW , Team,
Can you please clarify the below "SW tools for ADC35xx/ADC36xx" questions:
-What is the difference between those two SW? DATACONVERTERPRO-SW : https://www.ti…
Part Number: ADC3660EVM Other Parts Discussed in Thread: ADC3660 Hi,
SBAU356, Sep 2020, describes in Chapter 5 the HW modifications for external clocking:
DNI R176
replace C129 with 0R
DNI R32, R40
Install R36, R37
Connect sample clock to J8. Connect…
Part Number: ADC3660EVM Hi,
I tried to calculate the right DCLKIN values with the ADC35XX GUI 1.0 (or ADC3660EVM GUI, as it is also called).
The calculated DCLKIN values seem to be right for BYP or decimation factors up to 8.
For decimation factors of…
Part Number: ADC3660EVM Hi,
Just received the ADC3660EVM board for testing. The board seems to be an engineering prototype since many components have been reworked and there are some solder bridges, hanging components etc. I want to go over it and make…
Hi Matteo,
Oh yes, you are correct - my mistake. Thanks for reading up. NSD value should remain constant regardless of the decimation factor. If you divide the fs /16 in the excel calculator, then you will see the expected NSD is ~152 dBFS/Hz. I setup…
Hi Kelsey,
Yes you are correct, the ADC GUI does not print out the register writes for the CDCE6214 chip. CDC clock enable just enables / disables the onboard clock. If using external clocking, it is best practice to have it toggled off.
You can download…
Hi Ryan,
I set up the ADC3660EVM in the lab and configured it as you describe. I measured the FCLK duty cycle to be 50%. Can you read registers 0x20, 0x21, 0x22? These are the registers responsible for setting the FCLK duty cycle.
Regards, Amy