Chris,
Thanks for the answers. I have a few follow-ups:
That is what we observed. I guess I was just trying to point out that Table 6 was not clear about that.
Note that we are using the ADS1281 which does not have an internal mux. We are using an external…
Part Number: ADS1281 Other Parts Discussed in Thread: ADS1282 , DAC1282 Hi Team,
My customer is working with the ADS1281 and wants to design a built-in-test into his system in order to make sure the ADC is properly configured and ready to be used.
The…
Part Number: ADS1281 we are experiencing a problem during our start up process.
We are unsure whether this comes from the ADS1281 wakeup sequence or the CPU startup sequence.
Does the device have a "ready" flag to indicate it has completed startup and…
Part Number: ADS1281 Other Parts Discussed in Thread: ADS1263 , ADS1287 , ADS1283 , ADS1287D , ADS1282 Hi,
Today I want to buy ADS1281 on TI store.
But I saw this message in my cart.....
So what is the TI's recommendation to replace my datalogger on seismology…
Part Number: ADS1281 Other Parts Discussed in Thread: ADS1287 , ADS1262 , ADS1220 Dear, All
Customers are considering using ADS1281 and ADS1287. I would like to ask about the reference voltage and signal input voltage.
conditions:
AVDD = +2.5V, AVSS = -2…
Part Number: ADS1281 Hello,
Our customer use the ADS1281, have some questions about Sync timing.
I have included the questions in the attached file.
ADS1281_DRDY.pptx
Could you tell me the answer?
Best Regards,
Naoki Aoyama
Part Number: ADS1201 Other Parts Discussed in Thread: ADS1281 , I am trying to watch deeper in delta-sigma ADC for Python simulation I would make for board I'm designing (ADS1281, I need to take care of filters delay and phase)... but deeper I go, less…
Hello,
As promised, I am back to this subject after mounting a ADS1281 chip considered to have the unusually high amplitude low frequency tone on a channel that had another ADS1281 that didn't show the issue. We verify that the problem follows the…
Part Number: ADS1281 Hello,
I want to check about the tDR.
Refer to the Table 25 on the datasheet, when the fDATA=8ksps, the tDR=2824 x fCLK.
It means the tDR= 0.689ms using fCLK=4.096MHz.
Is it correct?
Best Regards,
Naoki Aoyama