Part Number: ADS54J20EVM Tool/software: Hi,
I have a ADS54J20EVM and wonder if there's a FPGA design available that I could migrate to ZCU102/106 (Zynq Ultrascale+)?
Best Regards,
Dominik
Part Number: ADS54J20EVM Dear colleague:
Our customer has below concerns:
1. Configuration file lmk_config_onboard_983p04_msps.cfg, is 983.04MSPS the sampling frequency?
2. The input signal power of AIN/BIN is required to be greater than 17dBm on…
Part Number: ADS54J20EVM Other Parts Discussed in Thread: LMK04828 , TPS82085 Hi Jim,
I bought the ADS54J20EVM last week,when i debugging i found no AVDD3.3 and 3.3VCLK..After circuit check i found the U12 was no power input and the U11 was not pasted…
Hi，RJH,
I think I have found the problem. The configuration file described in the ads54j20evm document is named lmk_config_onboard_983p04_msps.cfg, so I think the default CLK output of on-board crystal oscillator.So is the default operating mode for…
Part Number: ADS54J20EVM Hi Jim,
I still have some doubts,please help me confirm this：
1， In the section 9.2.1.1，as long as i choose the frequency of input signal，i can select the corresponding RC value and calculate the ZIN
2，At this step i’m not…
Part Number: ADS54J20 Other Parts Discussed in Thread: LMK04828 Hi jim,
The EVM did not work when i changed the balun translator,and the current is small .The voltage and input after balun are normal ,could you give me some suggestion for checking?…
Part Number: ADS54J20EVM Hi Team,
In ADS54J20EVM board layout, we found that analog diff signals length match for intra pair is 0.5 Mils and for inter pair between I and Q channels is 0.5 mils .
Do we require this length match for analog differential…
Part Number: ADS54J20EVM Other Parts Discussed in Thread: ADS54J20 Hi Team,
We observed that in the ADS54J** EVK, the terminations used for the analog signals is made as shown below for INAP, INAN, INBP and INBN signals:
In the datasheet of…
Part Number: ADS54J20EVM Other Parts Discussed in Thread: ADS54J20 In the reference schematics, we are seeing some intermediate voltage transitions to generate the needed voltage for the DAC. Any specific reason for this? Is it mandate to follow in our…
Peng,
Are you using the TI ADS54J20EVM with your FPGA board? If so, the configuration files that the GUI loads into the on-board LMK allows the device to provide the proper device clock and SYSREF signals after the file is loaded. You can use these…
