Part Number: ADS61B29 Other Parts Discussed in Thread: ADS4129 Both ADS61B29 and ADS4129 datasheets specify a MIN sine wave amplitude for clock input of 0.3v and 0.2v, respectively. However for a LVDS clock input only a TYP amplitude of 0.7v is specified…
Part Number: ADS61B29 Team,
I have a customer designing with ADS61B29, and they want to use the CLKOUT differential LVDS pair from the A/D as the main clock input clock for their FPGA (A/D is always on so no reason this CLK out couldn’t be the main…
Part Number: ADS61B29 Hi All
Here is the ADC design I done. I would like to get the design verified.
We have used 6 ADCs. Each ADC have its own voltage regulator. Clock is coming from same clock generator
It is a
I want to verify that the FPGA…
Part Number: ADS61B29 Hi,
We want to measure the noise floor of my ADC ADS61B29 (12 bit @ 50MSPS). For that we terminated the input of ADC and captured the digital samples using FPGA. We are having some doubts in the calculation. This is split into…
Other Parts Discussed in Thread: ADS61B29 Hi,
We are using ADS61B29 at 50MSPS in our board. We are feeding a input of 32.5MHz at -6dBFS. When we capture the digital data and plot it in wavevision, we are seeing a unexpected degradation in SFDR and…
Other Parts Discussed in Thread: ADS61B29 , ADS61B49 Hi,
When I configure ADS61B29 in Test pattern mode with "Outputs Toggle Pattern" , I'm getting first sample as 0xAAA and second sample as 0x555. The order is changing from capture to capture. What…
Other Parts Discussed in Thread: ADS61B29 I am using ADS61B29 for my project. Before fabrication I would like to perform the pre layout SI analysis of the ADC. From where will I get the IBIS model of the same . Can I use the available IBIS model of ADS61xx…
Other Parts Discussed in Thread: ADS61B29 Hi all,
I am using 3 ADS61B29 ADCs in my project. First one is getting an IF signal at 32.5MHz with a sampling clock of 50MHz. While the second one has 35 MHz input signal with 50 MHz sampling clock and the…
Other Parts Discussed in Thread: ADS61B29 I have the following question from a customer
" See page 21 of the ADS61B29 data sheet. When the CLKOUT position is adjusted via serial register 0x44 and shifted by +/- (4/26)Ts, is this shift relative to the…
Yes, cross reference recommends ADS61B29,ADS41B29, but INL and DNL are also not better than AD9233, and customer also don't need 100MHz sample rate, 50MHz is enough.
