Part Number: ADS8353 Hi,
In TI training videos, they all include noise from SNR figure. My understanding is that SNR is only a concern when input is AC.
In training, input seems to be DC. Why do we add Vn_ADC noise as input referred noise of ADC from…
Hi Matthew,
Thanks for your speedily reply! Here's some update that you might be interested.
I still want to use the SPI to interact with ADC and let McBSP to communicate with other peripherals.
After some modification with the FIFO register of SPI…
Part Number: ADS8353-Q1 Hi,
We are using ADS8353QPWRQ1 and is giving an external ADC reference voltage from an LDO through a buffer. The buffer output is fed to the ADC reference pin. The output broadband noise of the reference is filtered by a low-pass…
Part Number: ADS8353-Q1 Other Parts Discussed in Thread: ADS8353 Hi,
We are using 32 CLK single SDO mode with 3.3V external reference voltage. We feed the ADC input from an opamp output (single-ended) through an RC filter (100ohms, 2.2nF). We use SCLK…
Part Number: ADS8353-Q1 Hi
We are doing the noise analysis of ADS8353QPWRQ1 in which we are trying to calculate the total noise of the ADC system. We are performing the analysis based on the TI-precision-labs video: https://training.ti.com/ti-precision…
Part Number: ADS8353-Q1
Hello,
I have some troubles with the SPI interface of the ADS8353-Q1.
I have found out that I can correctly read and write the user programmable registers using SPI mode 1. In this case, the read data is shifted 1 bit left. The…
Part Number: ADS8353-Q1 Hello there,
about the acquisition time, the EC table says that the maximum acquisition time is tacq=33*tCLK-tconv= 33*50ns-730ns=920ns (when 20Mhz, dual SDO mode)
however, in figure 7-6 the tacq start at the end of tconv, ends…
Part Number: ADS8353-Q1 hello there,
my test result of SPI SDO data latched edge is opposite with the datasheet.
my test shows that the SDO latch edge is the rising edge of SCLK.
however, the datasheet(figure 7-7. and table 10) say that the latch edge…
