Part Number: ADS850
I just spoke with a customer with the following requirements:
Resolution > 12 bits
Speed >= 10MSPS
# Of channels = 3-5
After filtering the results there were a couple that met the resolution and speed requirements, but all…
Other Parts Discussed in Thread: ADS850 Hello!
I use ADS850 in our design. I saw timing diagram 1 in ADS850 datasheet. I attached a picture from datasheet. What kind of time region (1 or 2) suggest N sample? How much time needs to acquire input voltage…
Other Parts Discussed in Thread: ADS850 hi all,
this is Sharath, am using ADS850 in my design the problem is the cal busy pin is not getting low at any point of time my clk speed is 10Mhz. Vref is 1.8V
hi sorry for improper data attached file is design of our ADC. clk we are providing through FPGA . As per datasheet At starting it has to auto calibrate write.?(considering this we are not controlling it through CAL pin.).so is it mandatory to sense…
Thank you Josh. But I want to under-sample a 5MHz signal by a clock of 100KHz.. So my ADC must have some sample and hold circuit. I want a 14bit ADC like ADS850. But Evaluation boards are not available for that. So please can you suggest something like…
Hi Loren,
I can see my case getting worse if i replace C77 and C62 with 50 Ohm resistors and putting 50 Ohm resistors at R90 and R490. Output is getting halved but not significant effect on noise(or i should say no effect on SNR). I wanted to know…
Dear Everyone,
thank you all for your effort. I understand there are a lot of problems coming my way, but I can deal with mathematics and physics of the problem and the subsequent analysis (programming). I can have a system quite nicely running with…
Couple of quick things Akash,
1. Where is your DC bias current path for the V+ inputs to the op amps?
2. This differential I/O op amp circuit sometimes has a common mode oscillation - probably not here, but we did see that in the OPA838 decomp device…
