Part Number: AFE7900 Hello support team,
We are planning to design a custom AFE7900 board having same identical RF front end chain with the TCM2-33WX+ RF Balun in all 4 Rx channels ( RXA, RXB, RXC and RXD). For all other sections, we have taken a reference…
Hi David,
I'm closing this issue by stating resolved for configuration, and RX data was also captured by enabling RXTDD GPIO pins.
Will be opening a new issue for TX data.
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Regards
Vivek V
Part Number: AFE7900 My JESD & LMFS mode is JESD204B/24410,below is my problem:
1. If setting TX_LN_DATA_WIDTH is 32bit,What is the arrangement relationship of tx1_i0[15:0], tx1_q0[15:0] in tx_lane_data[31:0]?
2.If setting TX_LN_DATA_WIDTH is 64bit…
Closing this post, as it was answered via email:
Hi Benoit,
Matching the AFE or any HS ADC in the GHz input range is not an easy task.
ADCs in general have pretty poor return loss, so a simulation will give you a good first order direction what implement…
Part Number: AFE7900
I am trying to send a ramp test pattern on ADC. In order to do this, I have written a small piece of code in the Latte software.
AFE.JESD.ADCJESD[0].adcRampTestPattern(0,1,1)
When this function is called, I get the following prints…
Part Number: AFE7900 Hi,
I am using AFE7900EVM with zynq ultrascale + FPGA Board. Can anyone please let me know whether Xilinx JESD204B IP's are compatible with AFE7900 JESD204 Interface? If there is any difference please let me know
Thanks
Reg…
Hi Mubahsira,
The below lines can be ran to configure the ADCs into the alt 0/1 pattern. To change the pattern you can change the value you are writing to registers 0x109-0x10B. For example to enable the ramp pattern you would write 0x2 instead of 0x4…
Part Number: AFE7900 Hello Vijay,
thanks for your answer to my previous question.
Unfortunately, I was not able to see the attached picture. Could you please try to re-attach it ?
Also you mention in your message " Note that signal band of interest…
Hi Muhammad,
I believe the issue that you are facing is related to the data unpacking in your FPGA. Can you confirm that you are using the below format to unpack the data?
Regards,
David Chaparro