Part Number: AFE7900 Hi,
I am using AFE7900EVM with zynq ultrascale + FPGA Board. Can anyone please let me know whether Xilinx JESD204B IP's are compatible with AFE7900 JESD204 Interface? If there is any difference please let me know
Thanks
Reg…
Hi Mubahsira,
The below lines can be ran to configure the ADCs into the alt 0/1 pattern. To change the pattern you can change the value you are writing to registers 0x109-0x10B. For example to enable the ramp pattern you would write 0x2 instead of 0x4…
Part Number: AFE7900 Hello Vijay,
thanks for your answer to my previous question.
Unfortunately, I was not able to see the attached picture. Could you please try to re-attach it ?
Also you mention in your message " Note that signal band of interest…
Hi Muhammad,
I believe the issue that you are facing is related to the data unpacking in your FPGA. Can you confirm that you are using the below format to unpack the data?
Regards,
David Chaparro
Hi Tolga,
The bringup flow and power sequence for the AFE79xx are given in section 9.2 of the AFE79xx Configuration Guide. Please access this in the AFE79xx secure folder.
As we have been contacted through email we will close this post and reply over…
Part Number: AFE7900 Other Parts Discussed in Thread: AFE7901 , , Hello,
I am currently architecturing a new system based on an AFE7901 and a Xilinx Zynq UltraScale+.
Our need is to record then playback RF signals with a bandwidth of 140 MHz, that are received…
Part Number: AFE7900 Hi Experts,
Seeking your assistance on this query from customer:
[1] How to sampling the central frequency using the AFE7900 board? I have tried to sample a central frequency at 1.6G, but there is no anything on your software.
[2…