Part Number: AFE7950 Other Parts Discussed in Thread: AFE7900 , Hi, Rob,
Long time no talk! Good to see you here in the forum!
I'm also looking for the AFE7900 S-parameters, and noticed that there is an AFE7950 s-par file on the secure site, but the TX…
Part Number: AFE7900EVM Other Parts Discussed in Thread: AFE7900 Hi Experts, Good day.
I use the AFE7900 EVM.
If my ADC has a minimum full-scale power of -2.9dBm and a maximum full-scale power of 16 dBm. Does this mean that the power of my input signal…
Hi Tolga,
The configuration that you are using is combining the Sync signals into a single signal for all ADCs and that Sync signal is routed to the H7 and H8, it is not lane specific. Similarly all DACs are sharing a single Sync signal and that signal…
Part Number: AFE7900 Hello,
I am getting some errors while running the AFE7900 transciver.
Can you share the list of all Macro errors? (The macro error code I got is 0x13)
thank you
Hi Suleyman,
Timing requirements for the SYSREF are given in section 7.10 of the AFE79xx datasheet. I am checking with our team and what could be causing this issue to sometimes occur.
Regards,
David Chaparro
Part Number: AFE7900 Other Parts Discussed in Thread: TSW14J58EVM Hi team,
Here's an issue from the customer may need your help:
AFE7900 supports JESD204B, JESD204C, 8 SerDes transcevers up to 29.5 Gbps. With the TSW14J57, since the lane rate of J57…
Part Number: AFE7900 Hello everybody,
I'm planning the AFE7900 to measure the frequency spectrum of the DUT and to perform the Time Domain Analysis of the DUT like a VNA.
To do this, I would need to measure the initial phase of the AFE internal path…
Other Parts Discussed in Thread: AFE7900
I have a custom board design with AFE7900 and Xilinx Xcku050 FPGA.
I want to test my JESD lanes with registers B7h (DAC JESD - TX_JESD_TEST_S IG_GEN_MODE ) and 108h, 109h (ADC JESD - RX1_JESD_TEST_SIG_GEN_MODE…
Other Parts Discussed in Thread: AFE7900EVM , AFE7900 At present, I just bought AFE7900EVM and ZCU102EVB. I hope TI Support Team can send a complete vivado reference design project of FPGA on AFE7900+ZC102 platform.
Because this is the first time for me…
Hi Suleyman,
To enable the Rx PRBS for the 5th and 6th SERDES lane you should write 0x40 to address 0x16.
An example of writing to register 0x4084 is shown below:
device.writeReg(0x4285,0x00)
device.writeReg(0x4284,0x06)
To read registers in the SERDES…