Hi Derek, I've attached a basic block diagram of what I'd like to implement. The only outputs I need are at 10MHz. Among the slave devices is an FPGA, which can can derive any other clock frequencies I need from the 10MHz input.
Thanks for pointing…
Marco,
A free running clock that syncs to an optional input clock is a phase locked loop (PLL).
www.ti.com/.../products.html
I don't know which one that would have a center frequency with 5%, I suggest starting with CD74HC297
Other Parts Discussed in Thread: CD74HC297 , CD74HC7046A , SN74LS628 , LMX2582 , LMX2571 , LMX2541 , LMX2592 , LMX2594 , LMX2581 I'm looking for a VCO to produce a 12Mhz clock with a tuning range of at least +- 10000PPM . Cost is not a major issue. Simplicity…
Hi Mickey,
It would appear that the NE568A is an analog PLL. All of the PLL's in the Standard Logic portfolio are digital PLL -- ie they work on and generate square waves. We don't have a direct replacement.
I guess it's possible to replace an analog…
