For LVDS, common mode biase shoud be 1.2vx.
you can look at this document for more detail.
AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML.pdf
Best
Brian
Part Number: CDCLVP1102 Dear TI Engineer,
We are using the CDCLVP1102 to convert a 3.3 V, 10 MHz clock signal into an LVPECL signal, which is then fed into a clock device.
In the application report SCAA056 , the calculation methods for the termination…
Jayant,
You may be able to modify the FPGA_CLK output on the DAC3162EVM with some resistors to get the output to the correct LVDS level for the Xilinx device. See Figure 4 of the attached document.
Regards,
Jim
interfacing diff standards.pdf
Hi Surender,
The 1.2-V common mode voltage is part of the LVDS specification, so you aren't likely to find any LVDS devices with such a low common mode. The simplest solution in my opinion is to just use series capacitors to AC-couple the buffer's differential…
AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML.pdf
