• CDCLVD1208 - single ended use case and understanding datasheet jitter spec.

  

  Anjli Behl

  Other Parts Discussed in Thread: CDCLVD1208 RE: CDCLVD1208 questions 1) I am not using the differential input 0, should I connect the inputs as follows : INP0 - 1K pull-up to 2.5V supply rail ? INN0 - 1K pull-down to ground? 2) The spec mentions…

  • over 13 years ago
  • Clock & timing
  • Clock & timing forum

• LMK04610: LMK04610 and LVDS common mode

  

  Mickael Barre

  TI Thinks Resolved

  Part Number: LMK04610 Other Parts Discussed in Thread: CDCLVD1208 Hi, In Sysref output mode, to you have any recommandation to drive LVDS input with proper common mode ? Regards,

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• RE: LMK00101: Is there a TI Clock buffer which its input clk is 3.3v tolerable while its VDD powered by 2.5V ?

  

  Shawn Han

  Hi Ohad, Refer to 2.5V differential output clocks www.ti.com/.../products.html For example, CDCLVD1208 www.ti.com/.../cdclvd1208.pdf 3.3V LVCMOS input could be divided by resistors in 2.5V for CDCLVD1208 Best Regards, Shawn

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVD1216: Power supply for clock buffer

  

  Liren He

  Resolved

  Part Number: CDCLVD1216 Other Parts Discussed in Thread: CDCLVD1208 , Hi Ti experts, We have some doubts about power supply for clock buffer cdclvd1216 and cdclvd1208. As we search from the datasheet, there are no special requirements for power supply, such…

  • Resolved

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• RE: Power Dissipation of CDCLVD1208RHDT

  

  Arvind Sridhar

  Resolved

  Hi Suresh, Please see table on Page 5 of the datasheet: www.ti.com/.../cdclvd1208.pdf Supply current at Fin = 100 MHz and all outputs loaded = 62mA (Typ) and 84mA (Max). Power dissipated at 2.5V (mW) = 2.5V * 62mA Regards Arvind Sridhar

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum

• CDCE18005 total jitter at 10MHz

  

  Federico Cecili

  Other Parts Discussed in Thread: CDCE18005 , LMK00306 , CDCLVD1208 , CDCUN1208LP , LMK04828 , LMX2581 , LMK00304 , LMK00101 Hello, I would use a CDCE18005 as a reference clock mux and fan out buffer, and I would know the total jitter (possibly the max value)…

  • over 10 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• RE: Do unused output clocks on the CDCLVD210X and CDCLVP210X devices need to be terminated?

  

  Daniel Engeler

  Resolved

  How long can an open trace be? I have a CDCLVD1208 with a trace going to a connector which may be open or terminated.

  • over 10 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE72010 input hysteresis

  

  David Burton

  Resolved

  Other Parts Discussed in Thread: CDCE72010 , CDCLVD1208 Hi, The ref and VCXO inputs have a hysteresis option, but I don't see any discussion of exactly what the parameters of the hysteresis are. Is there some guidline on when hysteresis should be used…

  • Resolved

  • over 12 years ago
  • Clock & timing
  • Clock & timing forum

• RE: TLK1501 end point jitter question

  

  Matt Sunna

  Hi Jim, What type of cycle to cycle jitter is needed? From the measurements in the app note, the number could theoretically be close to 170ps (this may be a little pessimistic since the measurments in the app notes are peak to peak jitter). Since jitter…

  • over 12 years ago
  • Interface
  • Interface forum
Answered

• synchronizing CDCE72010 dividers across a large system

  

  David Burton

  Resolved

  Other Parts Discussed in Thread: CDCE72010 , CDCLVD1208 I have a system with 8 CDCE72010 clock drivers. I need to set up all the dividers and then have them synchronized over the entire system. I expect I need to use the nReset hardware input to do this…

  • Resolved

  • over 12 years ago
  • Clock & timing
  • Clock & timing forum

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