Part Number: CDCLVD2102 Hi,
I understand from the datasheet that the CDCLVD2102 is suitable for driving 100 ohm differential loads with its differential LVDS outputs. I would like to know if TI considers this part suitable to drive LVDS pairs over a long…
Part Number: CDCLVD2102 Hello, can I swap the P/N inputs and outputs? for example use INN0 as P input and INP0 as N input and then on the output also use OUTN as P output and OUTP as N output
As far as I understand this is possible but just want to make…
Part Number: CDCLVD2102 Hello,
Regarding to current consumption on CDCLVD2102, my customer is asking a question.
They use only two inputs(INP0/INN0) and remain inputs are connected to pulldown..
INP1/INN1：1K ohm pulldown
OUT2/OUT3：OPEN
(Question)
How…
Part Number: CDCLVD2102 From a single ended, 10MHz RF sine wave I need to generate a 10MHZ LVDS sine wave to feed a FPGA.
Is this feasible with the CDCLVD2101? If not what would you recommend?
Thanks, John Garrett TI-AFA
So if I am using LVDS standard as input to the buffer (with no caps) the data does not have to be DC balanced correct and then I can transfer also data rather then clock. Correct?
Other Parts Discussed in Thread: CDCLVD2102 Dear Team,
We received the below customer questions regarding the CDCLVD2102 device.
Please advise.
Kind Regards,
Mo.
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Dear Sir, I am facing a problem about some Clock Buffer device. The Part number: CDCLVD2102…
Other Parts Discussed in Thread: CDCLVD2102 Hello,
I have a customer that needs to drive an LVDS clock into a 1.2v bank (ddr4) in a xilinx ultrascale design. Do we have any collateral they could use to help in this? They're using a 2.5V CDCLVD2102 and…
Other Parts Discussed in Thread: CDCLVD2102 Hi,
I can see in the data sheet for the CDCLVD2102 that its "specifically designed for driving • One Input Dedicated for Two Outputs 50-Ω transmission lines. If driving the inputs in single • Total of 4 LVDS…
Part Number: SN65LVDS100 Other Parts Discussed in Thread: CDCLVD2102 , Hi,
I want to use this device for buffering a clock toward FPGA that have also phase noise input requirements (dbc values at several frequencies).
do you have a phase noise graph results…
