Part Number: CDCLVP110 Hi Expert,
We are working on using CDCLVP110VFR to replace the Renesas 853S111BYILFT.
The engineer is doing the evaluating and reported the CDCLVP110VFR output swing is too small.
Performance reading:
The target spec…
Part Number: CDCLVP110 Kindly advise the difference between CDCLVP110 M VFR and CDCLVP110VFR. Can't locate any detail in the datasheet as well as TI Website.
Hi,
In the datasheet,
Vcc=0V, Vee=-2.375V to -3.8V, Iee=min 45, max 82mA, Icc=max 370mA.
If use 6ch of 10ch, how can I calculate power consumption?
Do I have to do Iee+Icc*6/9?
Other Parts Discussed in Thread: CDCLVP110 What is the recommendation for dealing with unused clock inputs for the CDCLVP110? I could find no indication regarding the recommended terminated state (float, ground/hi directly, ground/hi through a resistor…
For LVDS, common mode biase shoud be 1.2vx.
you can look at this document for more detail.
AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML.pdf
Best
Brian
Hello Pengfei,
The closest we have in terms of frequency is:
LMX2582/92/94.
Over 4. Meaning 5 or more? These devices have two differential outputs. So if you consider each output single endedly, that would be 4 outputs, however the positive and…
Satoshi-san,
If customer just need 10 channel outputs, please recommend CDCLVP110. It is 10 output LVPECL buffer. This is better suited for what they want to do.
Hi Kato,
Is the fail safe a necessitate?
We have the CDCLVP111 and CDCLVP110 which will support your requirements except for the fail safe.
Is 3.3V a hard requirement as well or can you work with a 2.5V rail? We may have some other parts I can look…
Jayant,
You may be able to modify the FPGA_CLK output on the DAC3162EVM with some resistors to get the output to the correct LVDS level for the Xilinx device. See Figure 4 of the attached document.
Regards,
Jim
interfacing diff standards.pdf
