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Showing 14 results View by: Thread Post Sort by
    Answered
  • Re: Low Jitter clock distribution

    Fritz
    Fritz
    Resolved
    Hello Asad, the CDCM61001 + buffer IC will be a fine solution. You didn't indicate what signaling your inputs require. Is it LVDS, CML, LVPECL, or single-ended? If it's LVDS , you could use the CDCMVD110: http://focus.ti.com/docs/prod/folders/print…
    • over 16 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: Looking for a LVDS buffer with Vocm= 0mv to 300mv (user Defined) and Vout=200mv pk-pk

    Miguel Robertson
    Miguel Robertson
    Hi Surender, The 1.2-V common mode voltage is part of the LVDS specification, so you aren't likely to find any LVDS devices with such a low common mode. The simplest solution in my opinion is to just use series capacitors to AC-couple the buffer's differential…
    • AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML.pdf
    • over 14 years ago
    • Interface
    • Interface forum
  • Answered
  • CDCLVP110VF

    eli
    eli
    Resolved
    Can you please check the max T case allowed for the CDCLVP110VF?
    • Resolved
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum
  • Re: SN65LVDS104: fan out buffer 148.5MHz clock

    Miguel Robertson
    Miguel Robertson
    Sorry! Forgot to attach the app note. - Max
    • scaa059c.pdf
    • over 16 years ago
    • Interface
    • Interface forum
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