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Showing 20 results View by: Thread Post Sort by
  • CDCVF25081: PLL Bypass mode

    Timothy Starr
    Timothy Starr
    TI Thinks Resolved
    Part Number: CDCVF25081 We need a zero delay buffer in the clock path normally. However the zero delay buffers have a min frequency requirement that doesn’t work out for JTAG testing. I noticed that this part when the S2 pin is a 1 and the S1 pin is…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • CDCVF25081: Good Choice For High multiplication PLL?

    Bob Richardson
    Bob Richardson
    Part Number: CDCVF25081 Hi guys. I'm looking for a high multiplication solution for PLL. Would the CDCVF25081 be a good choice for a ~800,000X frequency multiplier PLL @ output ~50MHz ? The output Freq. is in the range i'm looking for, and i'm wondering…
    • over 9 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • CDCVF25081 vs IDT2309

    Takumi Suzuki1
    Takumi Suzuki1
    Resolved
    Other Parts Discussed in Thread: CDCVF25081 , CDCVF2509 Hi, My cutomer is planntin to use IDT2309. So I would like to propose CDCVF25081 to the customer against IDT2309. Because CDCVF25081 seems to be "pin-compatible" with IDT2309 without "pin16…
    • Resolved
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • CDCVF25081 16pin connection

    Takumi Suzuki1
    Takumi Suzuki1
    Resolved
    Other Parts Discussed in Thread: CDCVF25081 Hi, I would like to ask you 2 questions about CDCVF25081 16pin connection. Q1) Must 16pin be connected one of 8 outputs (1Y0 - 1Y3, 2Y0 - 2Y3)? If yes, for example, 1Y3(15pin) is very useful to connect…
    • Resolved
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • CDCVF25081 Cycle-To-Cycle Jitter spec

    Takumi Suzuki1
    Takumi Suzuki1
    Resolved
    Hi, I would like to ask you a question about the specification of "Cycle-To-cycle jitter vs Frequency"? There describes the specification on datasheet page8, fig 6. Is this spec applied to only "PLL mode" or both "PLL mode" and "Non PLL mode"? …
    • Resolved
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • About a case when CLKIN of CDCVF25081 disconnect suddenly.

    Satoshi
    Satoshi
    Resolved
    Other Parts Discussed in Thread: CDCVF25081 Please let me know about the operation on the output side when CLKIN of CDCVF25081 disconnect suddenly. Example ・After it is behind for a while (A few ms), turn off. ⇒After CLKIN turns off, how many "continueous…
    • Resolved
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • Re: Reflections with CDCVF25081 IBIS model - Regarding

    Bonnie Baker  - WEBENCH Design Center
    Bonnie Baker - WEBENCH Design Center
    Resolved
    Hithesh, In the IBIS file of this model the CDCVF25081_OUT is modeled. This output buffer is captured under the [Model Selector] section at the beginning of the file on line 88. In this statement, the buffer behavior of CDCVF25081_OUT is split into…
    • over 15 years ago
    • Simulation, hardware & system design tools
    • Simulation, hardware & system design tools forum
  • Answered
  • Zero delay clock multiplier with 2.5V, single end input/output

    Kawai
    Kawai
    Resolved
    Other Parts Discussed in Thread: CDCVF25081 , CDCVF855 , CDCE62002 Hello Team, Our customer is looking for a zero delay clock multiplier which could be used with 2.5V. Is there a 2.5V version device of CDCVF25081 ? I could find some zero delay clock…
    • Resolved
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • Advantage of Ti clock driver Vs. ICS?

    Bobby Jiang
    Bobby Jiang
    Resolved
    Other Parts Discussed in Thread: CDCVF2505 , CDCVF25081 , CDCV304 Dear, can you tell me advantage of Ti clock driver Vs. ICS as below form? thanks much! Type ICS's P/N TI 's P/N Clock Phase Lock…
    • Resolved
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: TLK1501 end point jitter question

    Matt Sunna
    Matt Sunna
    Hi Jim, This app note for the CDCVF2310 and CDCVF25081 is to show that these two clocking devices can meet the 40ps pk-pk jitter requirement for the TLK1501 reference clock input. The RX_CLK output from the TLK1501 device is recovered from the data…
    • over 13 years ago
    • Interface
    • Interface forum
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