Part Number: DAC11001B Hello Team,
I am confused with the headroom spec of DAC11001B.
On the datasheet, it says headroom/footroom spec to be 5V. However, if we set Vcc and VREF to be below, then we will be only be able to get 3V of head/footroom.…
Part Number: DAC11001B Tool/software: With the DAC11001 converter, the reference circuit is only bipolar, and we only use unipolar now, what kind of modifications can be made to the circuit? Or there is a reference circuit available. If the output is…
Part Number: DAC11001B Other Parts Discussed in Thread: OPA828 Tool/software: Hi, I created a circuit with the help of Some TI assistance and the resulting setup of the circuit bellow. The problem im noticing with the circuit is once the Device receives…
Part Number: DAC11001B Tool/software: Hi team,
I’m integrating the DAC11001B on a Linux host via SPI (Raspberry Pi Compute Module 4). I couldn’t find a Linux driver for the DAC11001B, so I’m looking for either:
an official or reference Linux…
Part Number: DAC11001B Other Parts Discussed in Thread: BP-DAC11001EVM Tool/software: Hello team,
Could you tell me output impedance value of SDO of DAC11001B?
The information helps to consider dumping resistor value.
Best regards,
Part Number: DAC11001B Other Parts Discussed in Thread: OPA827 Tool/software: Following the reference circuit on the DAC11001B pdf Document I am working on a schematic to use the DAC11001B in a configuration Such that its output voltage goes from 0-5V…
Part Number: DAC11001B Tool/software:
Applied to the unipolar output scene with output analog 0~5V, the schematic diagram is drawn in a bipolar way, and we want to change to unipolar. REFNF (5), REFNS(6) For these two feet I reserved two short ground…
Part Number: DAC11001B Tool/software: Hi All,
What is the settling time under the following conditions?
- VCC = +15 V, VSS = -15 V - Full-scale settling to ±1 LSB - VREFPF = +10 V, VREFNF = -10 V Thanks in advance. Regards, Toshi
Part Number: DAC11001B There is a section in the DAC11001B datasheet that states:
7.5.3.2 Asynchronous Update In asynchronous mode (LDACMODE = 0), data are updated with the rising edge of the SYNC (when daisy-chain mode is enabled, DSDO = 0), or at…
Part Number: DAC11001B Is there a time diagram for the generation of continuous signals where SYNC is always low and the values are loaded exclusively via Load? There is no timing for the the delay from the shift register input to output and there is…
