Part Number: DAC37J82EVM Other Parts Discussed in Thread: DAC38J84 Tool/software: Hi, I am having a problem trying to setup the DAC3XJ8X GUI, and getting the TSW14J56EVM to interface with the DAC3XJ8XEVM.
When I try and open the DAC3XJ8X GUI, I am…
Part Number: DAC37J82EVM Hi,
At the evaluation board :DAC3XJ8XEVM, we removed the transformer and try to use the single ended output.
However, noticed that there is a DC offset at the AOUTP and AOUTN.
can you please help where I can adjust the DC…
Part Number: DAC37J82EVM Other Parts Discussed in Thread: DAC37J82 On a Windows 11 Pro laptop, using the DAC3XJ8X GUI, I get the above problem when attempting to program the device.
I am running the same test set-up suggested in the Basic Test Setup…
Part Number: DAC37J82EVM HI,
we want to lock PLL2 in our evb.
our parameters in the following screenshots:
oscin- 100 MHz( extrnal clock mode).
what is the problem?
thanks
PLL2 only.
clock out from lmk(DAC Data rate)- 480 MHz( VCO 0…
Hello,
I would recommend you double check the power supply current if possible. See if you can notice any current changes between start-up and fully programmed by the GUI.
Each PC can only connect to one DAC37J82EVM by default. The default USB ID…
Part Number: DAC37J82EVM Other Parts Discussed in Thread: DAC37J82 Please pardon my ignorance! I would like to generate a ~375MHz tone out the DAC. It seems that the Quick Start files are limited to ~200MHz. Is there an easy way to generate and program…
Hi Kang, We have designed schematic for DAC37J82 output. Is it possible for you to review it and provide constructive feedback on it ? Thank you DAC37J82EVM had a 75 Ohm transformer but our application requires a 50 Ohm transformer TC1-1T-152X+ that has…
Part Number: DAC37J82EVM Other Parts Discussed in Thread: DAC37J82 , LMK04828 , DAC37J84 Hi,
I'm using the DAC37J82EVM alongside an FPGA board.
The clocking is set up as captured in the screenshot below.
The DAC37J82 is set up in 4-2-1-1 mode…
Hi Kang,
I tried modifying my sequence of commands before attempting synchronization like you suggested, adding in commands to reset the clock dividers before arming them. I didn't notice any difference in behavior though.
I am indeed using a gapped…
Good news!
I was able to successfully establish a JESD link between the DAC and FPGA without the DAC ignoring the ILA today.
The key was closely inspecting the link configuration data in the second multiframe of the ILA. I was able to find the details…
