Part Number: DAC37J84 I am generating two 100 MHz signal from DAC37J84 EVM channel A and B and measuring these in an oscillioscope. As shown in the below figure, I (channel A from DAC) is in green and Q (channel B from DAC) is in blue.
There are certain…
Part Number: DAC37J84 I am using the DAC in 250 MHz BW with 4x interpolation with the speed limit options as highlighted in the image below-
1. If I use the small fraction delay FIR filter will it reduce the BW further?
2. Is there any frequency response…
Part Number: DAC37J84EVM Other Parts Discussed in Thread: DAC38J84 Hi,
I am experiencing the same problems described in this forum http://e2e.ti.com/support/data-converters/f/73/t/815771?DAC37J84EVM-DAC3XJ8X-GUI-v-1-2-Link-Configuration-Issue .
When I push…
Part Number: DAC37J84 Other Parts Discussed in Thread: LMK04828 , DAC38J84 Hi Jim and Neeraj,
I checked the schematic and there is no resistor divider network other than 121ohm terminations on the clock lines.
As mentioned previously R179 & R180 are used…
Part Number: DAC37J84 I am interfacing DAC37J84 EVM with Xilinx ZCU102 Zynq board. I am seeing in chipscope that FPGA is sending "bcbc" characters for doing CGS. But DAC is not recognising "bcbc" characters and toggling SYNC accordingly.…
Part Number: DAC37J84 Hello team, My customer asks why there are typical values for "6.8 Timing Requirements" section in DAC37J84 datasheet. Is there any reason? How should the customer deal with those? Thanks, Nobuhiko Wasa
Part Number: DAC37J84 I used DAC37J84 EVM with Xilinx Zynq ZCU102 board. Below is my DAC configuration.
LMFS: 2441
DAC input rate: 250MSPS
Lane rate: 10Gbps
Interpolation: 4x
I observed that if I set K = 5 or 10 or 20 or 28, I am getting output.
For each…
Other Parts Discussed in Thread: DAC37J84 , DAC38J84 I used DAC37J84 and Intel altera fpga to transmit data. The CGS and ila phases seem to have passed, but my DA output waveform has many burr, but the frequency is corresponding. I read the value from 0x6c…
Hi Ebenezer,
We finally figured out the problem. It is independent from the configuration. In our hardware, there was a violation of the voltage levels for SYSREF signal. The output type was LVPECL_1600/2000. In EVM hardware, there is a voltage divider…
Part Number: DAC37J84 Hi,
I am using DAC37J84 evaluation board. Is it possible to generate a test analog signal using NCO & without FPGA interface?
If Yes, Please let me know how to do!
Thanks & Regards,
Swarup.