Part Number: DLPC3436 Other Parts Discussed in Thread: DLPA2005 , DLPA3000 My customer is developing DLPC3436 with DLPA2005, and the power-up timing requires that resetz should be pulled up after FPGA_1.8V for at least 10ms. The power-up timing on datasheet…
Hello,
We have a FW and SW package for the DLC3436, here . This is our FW selector tool. You just fill out information for the Controller and DLPA you are using.
The package for the DLPC3436 should have a FW .img file and a FPGA .bin file.
I don't think…
Part Number: DLPC3436 Other Parts Discussed in Thread: TIDA-080009 , DLPA2005 , DLPDLCR230NPEVM , TIDA-080003 PWM IN +RC filter is used as the comparator’s reference voltage and act as “ADC” for DLPC3436 by harvesting COM_OUT base on one of the input sources…
Seven,
You are welcome.
While there is not GUI intended to interface with the DLPC3436, there is a Python support package for the DLPC's EVM, the DLPDLCR230NPEVM. This package is available on the DLPDLCR230NPEVM Product page . Please keep in mind that…
Part Number: DLPC3436 Hello,
I can't seem to find the datasheet for the DLPC3436CZVB. When I open the page on the TI website ( https://www.ti.com/store/ti/en/p/product/?p=DLPC3436CZVB&keyMatch=DLPC3436CZVB&tisearch=search-everything&usecase=OPN…
Part Number: DLPC3436 The FPGA needs two LVDS to connect DLPC3460 then output Sub-LVDS signal to DMD.
1. The each channel of LVDS is in front of FPGA how many is the frequency to need?
2. How many is the Sub-LVDS output frequency?
Part Number: DLPC3436 if we understand correctly, the AP needs two LVDS ports to connect to FPGA in order to driver 1080p. The reason is that the standard LVDS interface supports 85Mhz clock (if I understand it correctly).
The AP we may choose to use…
Part Number: DLPC3436 Other Parts Discussed in Thread: DLPC3430 , DLP2010 , DLP230GP , DLP3010 The front-end chip (the host) connects to DLPC3436 through a Xilinx FPGA. The current FPGA software supports RGB or LVSD interface to the host.
Is it possible…