Other Parts Discussed in Thread: LMH0341 , LMH0340 , DS32EL0421 , DS32EL0124 Hi Team,
Our customer will replace LMH0340 to DS32EL0421 and LMH0341 to DS32EL0124.
There are several NC pins for DS32EL0421/0124. Would there be any problem for connecting…
Other Parts Discussed in Thread: DS32EL0421 , DS32EL0124 Hello,
My customer have some request about DS32EL0421 / DS32EL0124.
[Request 1]
Please provide me the output waveform of De-emphasis of DS32EL0421 like Figure 7-8 of LVDS Owner's Manual 4th…
Other Parts Discussed in Thread: DS32EL0124 , DS32EL0421 Hi,
we plan to use pairs of DS32EL0124 / DS32EL0421 in a future design. Is there some information around its life cycle? Or even an estimation for its EOL?
I'm asking because the design will…
Hi George,
You are correct. This pin requires a pull down resistor as described in the pin description section of the datasheet and also in Figure 11, the Typical Interface Circuit.
Glad you got everything working!
Mike Wolfe
DPS APPS / S…
Other Parts Discussed in Thread: DS32EL0421 , DS32EL0124 Hi Team,
Please tell me the recommended pull down and pull up resistor value for the logic inputs of DS32EL0421 and DS32EL0124.
I am reviewing customer's schematic and found 47kohm pull down…
Other Parts Discussed in Thread: DS32EL0421 Hi,
DS32EL0421 has the function of TXCLK delay adjust and it can be set to enable or bypass.
Then how is the setup and hold time set when the TXCLK delay adjust is bypassed by 24'h ?
Is it set to minimum…
Other Parts Discussed in Thread: DS32EL0421 , DS32EL0124 The register table on the DS32EL0421 datasheet does not specify the Readable or Writeable on Address 0x02 (Reset) bit 0 (Software Reset). Is this bit readable and Writeable? Is this bit self-clear…
Hi Mita-san,
Q1. The DS32EL0421 lock time is typ 10ms.
Q2. The DS32EL0124 lock time is only specified as reset to lock time, which does incorporate a small amount of power on time. The majority of the lock time is due to the CDR hunting through…
The serializer is specified from 125MHz to 312.5MHz (1.25Gbps to 3.125Gbps).
I want to ensure the following observations are correct
Since it is a LVDS DDR interface, without using DC balancing, the 5-bit inputs are used to create 10-bit words which…