Part Number: ADS1675 Good afternoon,
We're looking at using the ADS1675 for our design but could not find a specification in the datasheet that shows the relationship between clock jitter tolerance and SNR. Are there additional resources that show…
Hi Allen, Can you go into more detail - I fully want to understand what your question is here. Bit resolution is normally associated with ADCs. Clock jitter is tied to SNR. Typically, you want the highest performance clock to achieve the best SNR & performance…
Part Number: ADS4225 Hi teams,
I have questions about ADS4225 jitter.
I guess the clock jitter from CLKOUT is calculated from aperture jitter 140 fs.
It results in 1 / (140 * 77.7MHz) =92ps where fs is 77.7MHz. And it also equals t_jitter.
Is it correct…
Hi Adam,
We don't have an EVM for this ADC so I can't share a reference BOM. However, we do have an SNR vs Jitter excel calculator tool that can be used to show the SNR degradation when using a clock source with 100ps jitter, with a 100kHz input signal…
Hi,
The ENOB is affected by the Signal-to-Noise + Distortion Ratio.
There is a relationship between ENOB and input signal bandwidth. As the bandwidth of the input signal increases, SNR will start to decrease at some point due to aperture jitter in the…
Hi Mark,
Sorry for the delay.
I believe this is what you want confirmed...for this ADC device or any other ADC device with a JESD interface, you need a clocking tree as follows:
A clock to go to the ADC, the sampling clock and a ref clock, which is clock…
Part Number: ADS131M04 Hello guys,
One of my customers is considering using ADS131M04 for their new products.
They want to use MSP430 clock output (8MHz) as ADS131M04 CLKIN. But the clockoutput has about +/-3% jitter.
So they want to know how much SNR…
Part Number: ADC12DJ3200QML-SP Hi Team, We have a customer inquiry regarding figure 28 on page 29 of ADC12DJ3200QML-SP datasheet. 1. SNR is dependent on clock jitter. These are the measured results. 2. Do you know what the clock jitter is in these measurements…
Hi Giora,
I believe the papers that Eric suggested spells out how to do a jitter analysis on your clock distribution design.
Simply RSS (root-sum-square) each clocking device as they cascade to each other, the sum total jitter will be the jitter presented…
