Part Number: ADS131M04 Hello guys,
One of my customers is considering using ADS131M04 for their new products.
They want to use MSP430 clock output (8MHz) as ADS131M04 CLKIN. But the clockoutput has about +/-3% jitter.
So they want to know how much SNR…
Part Number: ADC12DJ3200QML-SP Hi Team, We have a customer inquiry regarding figure 28 on page 29 of ADC12DJ3200QML-SP datasheet. 1. SNR is dependent on clock jitter. These are the measured results. 2. Do you know what the clock jitter is in these measurements…
Part Number: ADS5294 Other Parts Discussed in Thread: LMK04826 I am aware of the relationship between sample clock jitter and SNR. If I am using a clock generator device, what I am unclear about is which of the jitter specifications I should be using…
Part Number: PCM1794A What is the max jitter specification required on SCK3 in order to meet the specified SNR (say -125dB @ 17kHz)?
For example, with a 48kHZ sample clock (SCLK3 = 18.432MHz, 384Fs) and an output frequency we calculate the jitter needed…
Other Parts Discussed in Thread: ADS42LB69 Hello,
In the datasheet of ADS42LB69 , there is the Figure 22 SNR versus Input Frequency and External Clock Jitter. And there the 5 curves which have jitter from 35fs~200fs.
<Question 1> Is this Figure calculated…
Hi Carlo,
There will not be any performance difference between free-running or stop-clock operation. The SPI format is limited to 27MHz and trying to operate faster than that is likely to result in insufficient setup and hold times and it is possible…
Hi Balaji,
The XI clock is the reference clock for PHY, so jitter in this clock results in jitter for transmit and receive clocks of the PHY as well as a degraded SNR.
Does this answer your question?
Thank you,
Nikhil
All information in this correspondence…
Part Number: ADS1672 Hi team,
We got inquires from customer as following.
Duty cycle of CLK In case of multiple conversion, customer will configure ADS1672 CLK = 20MHz, FastResponse, LowLatency, DR=625ksps. According to the datasheet, the duty cycle…
