Part Number: LMH1982 Other Parts Discussed in Thread: LMH1983 , Tool/software: Do you have phase noise measurements for SD_CLK and HD_CLK? I'd like to know if the performance is similar to the LMH1983 CLKOUT1 and CLKOUT2/3.
Part Number: LMH1982 Other Parts Discussed in Thread: LMH1983 , Hi team,
The output clock frequency will change if we turn on/off GENLOCK, and it is not acceptable. Do you have any method to decrease the frequency change?
Best, Zeming
Part Number: LMH1982 Other Parts Discussed in Thread: LMH1983 , Hi team,
Is the PLL in LMH1982 same with PLL in LMH1983? Because if they are same or similar, they can utilize LMH1982 as an alternative of LMH1983.
Best regards,
Shunsuke Yamamoto
Part Number: LMH1982 Other Parts Discussed in Thread: LMH1983 , Hi team,
LMH1983 has auto format detection function, does LMH1982 have similar funtion?
Best, Zeming
Part Number: LMH1982 Hello Experts, I have a question. The table 2 in the datasheet shows known supported standard timing formats. Can this device support other formats? (such as VGA Hsyc 31.469KHz?) Best Regards, Fujiwara
Part Number: LMH1982 Hi Team, May I ask for help? My customer concern is as shown below: " I saw LMH1982 but it doesn't support 4k60 video. The genlock application I want to use with video scaler IC deals only with V_sync not H_sync. However, LMH1982…
Part Number: LMH1982 Other Parts Discussed in Thread: LMH1981 hello, we are using LMH1982 to generate video clock generator with genlock， but we failed to make the video genlock and synchronization to work. please refer to below information. we get the…
Part Number: LMH1982 Other Parts Discussed in Thread: LMP7711
Hello I have the strange problem reported here https://e2e.ti.com/support/interface/f/138/p/542596/1981841?tisearch=e2e-sitesearch
Did anyone solve it or is it a bug? Thank you.
It should be OK to maximize the ICP1 value to test if it helps reduce PLL PFD input phase offset due to leakage on the Vc node. This will increase the BW and DF slightly.
Besides VCXO input impedance, another potential leakage path is leakage loop…
I suggest to try the following:
1) Generate Output TOF timing using the 27 MHz SD clock frequency domain (TOF_CLK=0 ,SD_FREQ=0) instead of the native HD clock frequency. Follow "Option 2" example in datasheet section 8.1.6.2.2.1.
2) While PLL1 is…
