Part Number: LMK01801 Hi,
Is there any frequency limitation when feeding a single ended input clock to CLKin0 or CLKin1 pin more constraining than the "0.001 to 3100 MHz" frequency range (considering CLKin_MUX = Divide CLKinX_DIV = 2 to 8)?
Thank…
Part Number: LMK01801 Hello.
Please could Ti provide min and max propagation delays for the LMK01801. Only a typical is provided.
I need to know this as I have a requirement for the propagation delay in my design.
I appreciate the help.
Part Number: LMK01801 Hi,
I design a board with a LMK01801 configured in PIn Mode (En_Ctrl_Pin = High) as described in Table 3.3 of the Datasheet.
I have some trouble with the divider on CLKout12 and 13 which are configured in :4 (CLKoutDIV2=LOW). Sometime…
Part Number: LMK01801 Hi team
I know the inpi know the input output freq range 1khz to 3Ghz, but the microwire (SPI) operating frequency and the speed how much?ut output freq range 1khz to 3Ghz, but the microwire (SPI) operating frequency and the speed…
Hi,
You have selected TMS470R1A256 as the part number when you created the post. The TMS470R1A256 is a MCU which does not have the capability to divide your clock input (76.8Mhz) into 38.4Mhz. Please take a look at the below clock divider IC to see if…
Part Number: LMK01801 Other Parts Discussed in Thread: LMK61E2 Good Morning/Afternoon Texas Instrument Support.
Thanks for your time and support until now.
I have already read https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing…
Part Number: LMK01801
Hello Team,
do we have a way to read back the register from the LMK01801?
What would you recommend to make sure that the registers are written properly?
Thanks,
SunSet
Part Number: LMK01801 We are using following TI clock buffer in our design.
LMK01801 Dual Clock Divider Buffer.
We have two queries during testing facing some issue with the clock divider output,
Issue : 1
Clock divider input <= 2.5GHz ,we are getting…
Part Number: LMK01801
Hi, I want to divide a ~2.5GHz clock source by 4 using the LMK01801. The datasheet specifies 50 fs additive jitter at 800 MHz (12 kHz to 20 MHz). Is this the case regardless of input frequency and clock division? (Or specified for…