Answered

• RE: LMK1D1216: Additive jitter of Clock Buffer

  

  Michael Srinivasan

  Resolved

  Hi Genrikh, I have attached two phase noise measurements. The first is the baseline measurement - it is the phase noise plot of the output from an SMA100 signal generator. The second is the measurement from the output of the LMK1D1216EVM. The additive…

  • 1 month ago
  • Clock & timing
  • Clock & timing forum

• LMK1D1216: LMK1D1216

  

  Chetan Karkera

  TI Thinks Resolved

  Part Number: LMK1D1216 Tool/software: Hello, Any document which gives clear information on the power consumption and temperature generated on the LMK1D1216 die when all the 16 outputs are enabled for 1.8V, 2.5V and 3.3V?

  • 8 months ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK1D1216: LMK1D1216 power consumption

  

  Chetan Karkera

  Resolved

  Part Number: LMK1D1216 Tool/software: Hello, Any document which gives clear information on the power consumption and temperature generated on the LMK1D1216 die when all the 16 outputs are enabled for 1.8V, 2.5V and 3.3V?

  • Resolved

  • 8 months ago
  • Clock & timing
  • Clock & timing forum

• LMK1D1216: Can ONE input signal (IN0) fan out to ALL 16 Output Channel pairs?

  

  Thomas McCoy

  TI Thinks Resolved

  Part Number: LMK1D1216 Other Parts Discussed in Thread: LMK1D2108 Hi, I am reading the documentation here and here for this board and I can't tell whether one input signal (IN0) is capable of fanning-out to all 16 output channels or if IN0 is restricted…

  • 11 months ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK1D1216: Obtaining ultra low jitter fanout for LVDS signal pulses/ low frequency input

  

  Boris van Wessel

  Resolved

  Part Number: LMK1D1216 Hello! For an implementation with a super fine resolution TDC i am looking for a method of fanning out 1 LVDS input pulse to 16 LVDS pulses in order to do sample averaging on the TDC. The implementation of this fanout/repeater…

  • Resolved

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK1D1216: Effect of Unterminated LVDS Outputs

  

  David McLaurin

  Resolved

  Part Number: LMK1D1216 Hello, I have an application where they can be any number (0 - 16) of devices downstream loading/terminating the clocks generated by this LMK1Dxxxx and I'm trying to understand the performance impact that I would see when a number…

  • Resolved

  • over 2 years ago
  • Clock & timing
  • Clock & timing forum

• SN65MLVD203B: MLVDS differential input range

  

  Chetan Karkera

  TI Thinks Resolved

  Part Number: SN65MLVD203B Other Parts Discussed in Thread: LMK1D1216 , Tool/software: Hello, I am working on the project where LVDS splitter LMK1D1216 output is connected MLVDS( device unknown for now) receiver. For example if i take SN65MLVD203B as a MLVDS…

  • 6 months ago
  • Interface
  • Interface forum

• RE: LMK00301: What to do about optionally terminated outputs

  

  Jeffrey Limbocker

  Hi Will, I had read on a post about a similar part ( LMK1D1216 ) that there could be performance degradation on adjacent channels. Is this part not susceptible to the same problems? I just want to confirm that there will be no impact to the phase noise…

  • 8 months ago
  • Clock & timing
  • Clock & timing forum
Answered

• RE: CDCDB2000: CDCDB2000 minimum frequency

  

  Borge Strand-Bergesen

  Resolved

  Thank you! I will have a close look at the LMK1D1216. Best, Børge

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCUN1208LP: Cascading buffers

  

  Mark Cianchetti

  Resolved

  Part Number: CDCUN1208LP Other Parts Discussed in Thread: LMK1D1216 , CDCLVP1216 I couldn't find any documentation on whether these buffers can be cascaded. Is there anything besides additive jitter/propagation delay that would disallow cascading two…

  • Resolved

  • over 2 years ago
  • Clock & timing
  • Clock & timing forum

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