Part Number: LP8764-Q1 I am attaching the JSON file for my project
I am able to see the watchdog error register Device address 0x12, register address 0x08 read value of D2. But the nRESETOUT_SOC signal (mapped to GPIO5) does not go low.
GPIO4 is mapped…
Part Number: LP8764-Q1 In a 4-Buck configuration, I noticed that for a quick Off-On control (140ms or less), the Buck1 has not discharged below Residual Voltage (RV) threshold, hence the PMOIC won't power on.
After RV is disabled for Buck1 in static…
Part Number: LP8764-Q1 I would like to know how the current limit works during normal and startup operation. In one of my applications I have a 1.2V output , Lout=1uH, Fsw=2.2MHz in FPWM mode and with slew rate set at 10mV/us. With this slew rate, the…
Part Number: LP8764-Q1 I am using GPIO4 as an active high enable to sequence the rails and go to active state.
If the Watchdog is enabled in NVM, Does the long window start automatically when the NVM finish loading, even though the enable pin (GPIO4 in…
Part Number: LP8764-Q1 Hi Team,
A few quick question about using a GPIO as VMON for LP876X.
1. If a GPIO is reconfigured for VMON functionality after startup will PU/PD resistors be disabled automatically or do these need to manually be disabled? (NVM…
Part Number: LP8764-Q1 Team,
Can you confirm that it is accurate that setting GPIO8_SEL to either 10b or 11b set GPIO 8 function to VMON2? I found the redundancy strange so wanted to confirm this wasn't a typo.
Part Number: LP8764-Q1 Hi team,
Customer is using LP876411B4 for TDA4 power, would you please help share the demo code for LP876411B4?
Thank you
Scarlett
Part Number: LP8764-Q1
a) When the PMIC is functional ? Is there a way to read the current FSM state where the device is working now ?
b) Four I2C address are taken up by a PMIC device. How are the addresses provided in the register map assigned across…
Part Number: LP8764-Q1 Hi team,
According to PDN 1A, LP876411B4 working together with TPS65941213. GPIO 4 of LP8764 is the optional way to enable LP8764 (primary enable way is by SPMI). We will not use this feature, what is the suggestions for this pin…
Hi Kai,
I do not see any issues using soft reboot functionality from my side. Please read interrupts before and after writing soft reboot.
Thanks,
Daniel W