Part Number: DS90LV027A Hi,
We are facing some Voltage Level issue with LVDS. In our case we have to setup an LVDS communication with an FPGA EVK to our DUT. DUT LVDS line is 2.5V. The FPGA pins which is available in FMC connectors is at 1.2V level…
Other Parts Discussed in Thread: LMH0340 , LMH0341 , LMH0394 , DS125RT410 Hi
Goal : Total throughput 40 * 148.5 = 5940Gbps => 1188Gbps / LVDS DDR Link which is compatible with XILINX serie 7 IO of KINTEX and ARTIX
Advantage : 12 / 40 (30%) pin ratio…
Other Parts Discussed in Thread: DS15BR400 , DP83620 , DP83620-EVK , DP83849IF , DP83849IFVS-EVK Hi everyone,
I have an in-house built optical transmitter (LED) and ROSA (PIN & TIA) that we are developing as our optical link. I would like to demo this…
hi Jaime,
Just did a quick measurement on a LMK04816 EVK with Clock Group 0, 1 and 5 are LVPECL, Clock Group 2, 3 and 4 are LVDS. OSCout is LVPECL. Typical current on each Vcc pin is as follows:
Vcc1
90.46mA
Vcc2
85.28mA
Vcc3…
Mark,
We don't have an easy way to use I2C right now but I think we figured out the problem. I believe our EVK was modified from the default configuration before we received it. We had some components (mostly resistors) populated that were shown not…
DLPLCR9000_DMDBOARD_P9_WQXGA_TYPE_A_1 (1).pdf
I am referring to page 4 of the attached schematic.
During normal Enable OFF condition, Why do we need to connect VOFFSET to Zener via 12 ohm resistor.
Thanks,
Muni
Part Number: DS90UB941AS-Q1 Other Parts Discussed in Thread: ALP ,
Dear TI team,
We are working on serializer (DS90UB941AS) and De-serializer (DS90UB948Q) with i.mx8QuadMax processor based custom board.
Our serializer configuration is as below …
Takahashi,
Here is some more info that I hope helps you with your issue:
Regards,
Jim
Make sure the mode (Bytewise/Wordwise, 14b/16b/18b) set in the device GUI matches with the INI file selected in HSDC pro. Some information about Frame clock…
