TI E2E support forums
TI E2E support forums
  • User
  • Site
  • Search
  • User
  • E2E™ design support >
  • Forums
    • Amplifiers
    • API solutions
    • Audio
    • Clock & timing
    • Data converters
    • DLP® products
    • Interface
    • Isolation
    • Logic
    • Microcontrollers
    • Motor drivers
    • Power management
    • Processors
    • RF & microwave
    • Sensors
    • Site support
    • Switches & multiplexers
    • Tools
    • Wireless connectivity
    • Archived forums
    • Archived groups
  • Technical articles
  • TI training
    • Tech days
    • Online training
    • Live events
    • Power Supply Design Seminar
  • Getting started
  • 简体中文
  • More
  • Cancel


Search tips
Showing 11 results View by: Thread Post Sort by
    Answered
  • PLL1707: TI Support for new design

    Kazuki Itoh
    Kazuki Itoh
    Resolved
    Part Number: PLL1707 Other Parts Discussed in Thread: CDCE813-Q1 , CDCE6214-Q1 , CDCE913-Q1 , , TM4C1290NCPDT Hi team, Does TI support PLL17XX for new design? I'm worried if I can recommend this to the customer because this is old audio PLL. Also…
    • Resolved
    • over 6 years ago
    • Clock & timing
    • Clock & timing forum
  • PLL1707: How to synchronize two audio clock domains?

    Geza Balazs
    Geza Balazs
    TI Thinks Resolved
    Part Number: PLL1707 Other Parts Discussed in Thread: DS90LV011A , DS90LT012A Dear TI Technical Support, I am in the design phase of a high-end analog audio front-end module that will utilize PCM4220s and PCM1794As that are clocked by a PLL1707. I have…
    • over 7 years ago
    • Audio
    • Audio forum
  • Question of PLL1707 Lock issue

    BRIAN PENG
    BRIAN PENG
    Other Parts Discussed in Thread: PLL1707 , PCM1798 Dear Sir: I am now using PLL1707 "SCKO3" to be a clock source for my FPGA's clock source to generate sck, bclk and lrck of PCM1798. The clock output waveform at trigger position is as figure1. …
    • over 13 years ago
    • Audio
    • Audio forum
  • RE: TPIC8101: Alternative solution for frequency lower than 1.22kHz

    Mason's
    Mason's
    Thanks. Can you recommend a TI PLL to use in this low frequency application? PLL1707-Q1?
    • 6 months ago
    • Interface
    • Interface forum
  • Answered
  • RE: DIX4192: jitter reduction by DIX4192?

    Brian Coykendall
    Brian Coykendall
    Resolved
    Hi Zak, Our PLL/VCXO is a PLL1707 driven by a very low jitter VCXO, whose control voltage we have heavily filtered. The 24.576MHz and 22.5792MHz outputs of the PLL1707 are fed directly to a CPLD, where we use the 24.576MHz for the DIX4192's RXCKI. I…
    • over 5 years ago
    • Audio
    • Audio forum
  • Answered
  • RE: LMK03806: Options for generating <1MHz clocks (I2S LRCLK)

    Lane Boyd
    Lane Boyd
    Resolved
    Hi Pavel, Have you taken a look at PLL1707? It generates 256*fs and 384*fs clocks, it could work with well with a divider as you suggested. These frequencies are all unrelated. They would be difficult to synthesize from a single VCO as the VCO would…
    • over 6 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: PCM3168 and mcasp0 of sitara processor (BeagleBoneBlack)

    Pablo Fonovich
    Pablo Fonovich
    Hi: As nobody answered, i'll propose a solution, and i want to ask if it's ok... what if i use PLL1707 to generate the clock and connect it to SCKI of the PCM3168? Should i also connect it to mcasp0_ahclkr and the mcasp0_ahclkx to syncrhonize it all…
    • over 11 years ago
    • Audio
    • Audio forum
  • Answered
  • TAS5518C and jitter

    Constantine Musatoff
    Constantine Musatoff
    Resolved
    Other Parts Discussed in Thread: PLL1707 , TAS5518C TAS5518C has 2 clock inputs: master and bits. Jitter of bit clock or master clock is more influence on sound? Master clock I obtain from quartz generator on PLL1707 and bit clock from DSP. I can pass…
    • Resolved
    • over 14 years ago
    • Audio
    • Audio forum
  • Answered
  • Build low jitter audio clock with air (WiFi) sync

    Constantine Musatoff
    Constantine Musatoff
    Resolved
    Other Parts Discussed in Thread: PLL1707 , CDCE913 , DAC5571 AirPlay or DLNA protocols send clock information from time to time. Because of uncontrolled delays, this clock information has very large jitter. I can cancel it by program algorithm with analyzing…
    • Resolved
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • PCM3168A

    wendelin klimann
    wendelin klimann
    Resolved
    Other Parts Discussed in Thread: PCM3168 , PCM3168A , PLL1707 Hello I am implementing an PCM3168A Audio Codec into the BeagleBoard by using the ALSA framework. And so far i got my first audio signals out of the PCM3168 :-) Till now i use the hardware…
    • Resolved
    • over 13 years ago
    • Audio
    • Audio forum
>

Didn't find what you are looking for? Post a new question.

  • Ask a new question