Part Number: TL16C554 Tool/software: Linux Dear TI Team,
Can I provide the Linux driver for the TL16C554?
We expect the data to be intermittently broken and a software problem.
Ask if you can get a linux driver.
Thanks.
Other Parts Discussed in Thread: TL16C554 Hello, all
Now we have one inquiry regarding baud rate description on TL16C554 from our customer.
Please refer to the item below, and feedback us with your comment.
When referring page 26 to 28 (Figure 8 to 11)…
With the UART in RS422/485 mode and the serial port disabled via the driver what should be done with unused pins. The 3 signals in question are ‘CTS#’, ‘DCD#’, and ‘RI#’, should they be terminated in some way?
These…
Hello Stephan,
I apologize for the delay in responding. The only changes from the TL16C554 to the TL16C554A are the 3.3V operation support and the addition of the Autoflow (AFE) capability. The TL16C554A has the same pinout and can be used as a drop…
Part Number: OMAP-L138 Other Parts Discussed in Thread: DA8XX , TL16C554 , PMP Tool/software: Linux We are using Omap l138 with arm running Linux (kernel 3.3) and DSP running TI-RTOS with Syslink. When arm does a file write it seems that DSP is unable to…
Hi Praveen,
I apologize for the delay in responding to your question while I did a little research. I wanted to make sure I gave you a correct answer.
I believe that I can safely determine that the TL16C754B is 16550 compliant and a good option to…
Other Parts Discussed in Thread: TL16C554 , AM3352 Dear Champion,
Today I received one issue related with the AM3352 UART usage. The OS is Linux SDK 7.0. Customer use 4 UART ports in their design. In addition, they also used the TL16C554 to extend 4 UART…
Hi:
Thanks for your answer. I am sorry for my questions are not clear .
1. We will connect TL16C554 to the Lanchpad, can you suggest us?
2. Our application is expand the UART with TL16C554.
3. The reference code we already studied. We need some…
The TL16C554 datasheet says:
INTA, INTB, INTC, INTD: External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and inform the CPU that the ACE has an interrupt to be serviced. […] The interrupt is disabled when it is…
