Part Number: TPS3430-Q1 Hi Teams,
1. The default expected power on state is SET0 high level (external pull-up 10k), SET1 low level (external pull-down 10K), disabled state (CWD=NC, SET0=1, SET1=0 Mode), then after the program initialization is completed…
Part Number: TPS3430 Hi,
I am using the TPS3430 window watchdog timer IC in a design to control the power-on-reset of my board.
Watchdog Supply ( VDD ): 5V (always alive)
Watchdog Output ( WDO ): Connected directly to the Enable (EN) pin…
Part Number: TPS3430-Q1 I performed several tests on the watchdog device and observed some unexpected behavior on the WDO output. Below is a summary of the test conditions and observations.
Test Observations
I observed that the WDO pin remains HIGH…
Part Number: TPS3430 Other Parts Discussed in Thread: TPS35 , TPS3435 Hi, I'm looking for watchdog timer which have long period after reset timeout period. (What I mean is kind of "tRST" after VDD(min) on following figure.) I need 4s - 5s period. However…
Part Number: TPS3430 Other Parts Discussed in Thread: TPS3435 Tool/software: Hi Team
do we have any replacement for STWD100NWWY3F?
https://www.st.com/resource/en/datasheet/stwd100.pdf
BRs
Brian
Part Number: TPS3430 Hi team,
we had integrated tps3430 WWDOG timer, based on configuration:
and calculated tWDU=62.74ms, tWDL=7ms and tRST=0.70ms.
I'm implementing code in such a wat that after enabling WDOG using SETx pins(only possible condition…
Part Number: TPS3430 Hi team,
My customer has two questions regarding TPS3430, can you help advise?
1. In the datasheet, it shows that,
To achieve the latching watchdog feature, an open-drain buffer is connected from WDO to CRST with a small value…
Part Number: TPS3430 Tool/software: Hi,
We are using the TPS3430WDRCR part in our design. We used 5V as supply voltage for VDD1 and VDD2.
Can we use 5V supply to SET0 pin with pullup resistor and 1.8V supply to SET1 pin with pullup resistor?
Regards…
Part Number: TPS3430-Q1 Tool/software: Hello teams,
We use TPS3430-Q1 in our design ,we want to reset Watchdog， the design like this picture. is it OK?
The WDO is high when the VDD1 and VDD2 is low, is it right?
Part Number: TPS3430 We are using TPS3430 watchdog timer which is connected to the SoC. The input for the watchdog timer would be a pulse signal. Is there any sample code/library file that can be used in the SoC, so that the tps3430 can get the input…
