Hello,
It is my understanding that after 1 sec of all the rails coming on the PGOOD signal will activate. Is this correct? If so, is there a way to adjust this time? I saw on another thread ( ) that changing the EEPROM could change the PGOOD time. Is this…
Part Number: TPS65261 Hi,
I'd like to know following 2 questions about recommended capacitor value on V7V that was changed from 1-μF to 10-μF, discussed in previous thread.
https://e2e.ti.com/support/power-management-group/power-management/f…
Part Number: TPS65251 Hi,
I'd like to ask about averaging model of TPS65251 in Tina.
I'm making stability plots and don't know why:
1. Phase plot starts from 100deg?
2. Phase margin is calculated by Tina in respect to 0deg Phase, not 180de…
Part Number: TPS65251 Hello guys,
One of my customers is designing a power supply using TPS65251.
At this moment, they have the following question.
Could you please give me your reply for them?
Q. We calculated Cff using equation 15 shown on page 19 of…
Hi Eric,
Thanks for reaching out to us.
1. Do you mean that customer uses three TPS65261. The first one uses two Buck output(3.3V, 1.8V), the second one uses two Buck output(3.3V, 1.8V), the last one uses one Buck output(3.3V)? However, for the last one…
Part Number: TPS65251 Hi Team,
Could you show the difference between TPS65251 and TPS65251-x, as well as difference between TPS65251-1, TPS65251-2 and TPS65251-3?
I looked at the datasheet but didn't find...
thanks a lot.
Best regards,
Yang
Part Number: TPS65251 Hi,
Per our datasheet and EVM user guide, our recommend resistor for the CMP pin is 20k, 0.1% accuracy.
Could we use 1% accuracy resistor in stead of?
Thanks.
BR
Mason
Part Number: TPS65251 As per our requirement, we are using two outputs of TPS65251. Buck 1 : 3.3V & Buck 2 : 1.2V.and PGOOD for power status in our design.
Buck 3 is properly disabled by pulling low to the EN3 pin,
Even though we are disabling Buck…
Hi, Jordan
I review your schematic, it is okay, but layout is bad.
I think the issue is caused by bad layout, suggest place 30ea VIAs at thermal pad.
I attached a layout guideline for your reference.
TPS6525x_LAYOUT_GUIDE.ppt