Part Number: TPS68470 Dear TI member,
We are using TI/TPS68470YFFR and have below question
1.
(1)Could HCLK_A pin of TI/TPS68470YFFR output 19.2M Hz?
(2)Would you mind to let us know how to set it?
2.TI/TPS68470YFFR is implement for rear camera application…
Part Number: TPS68470 I am using TPS68470 in one of our design, i am not using Buck from this PMIC.
Any termination guidelines if Buck is not used. Specifically these G7 and H6 pins.
Part Number: TPS68470 Hi,
Is there any possibility to achieve HLK_A and HCLK_B clock rate as listed below with source from either GPIO3 or crystal? Or the clock rate of them must be in the range from 4M to 64MHz anyway?
1. HCLK_A: 24 MHz
2. HCLK_B: 32…
Part Number: TPS68470 Hello,
One of my customers is using TPS68470 on their design and are not using buck from this PMIC. Are there any termination guidelines for the pins not being used, specifically the ones highlighted below:
Thanks,
Nitish
Part Number: TPS68470 Hi TI team,
We are using TPS68470 PMIC for one of our smallest camera boards.
While powering the board on, we are seeing the PLL lock time out issues .
Once lock timeout happens, the driver shuts down the PLL and shuts down all the…
Part Number: TPS68470 Other Parts Discussed in Thread: TPS65000 Hi,
Customer needs PMIC solution similar to TPS68470 but for single port camera. The requirement as below. Do we have good fit product?
1. 2.8V/20mA.
2. 1.8V/3mA.
3. 1.2V/54mA.
P.1.pdf …
Part Number: TPS68470 Hi,
Customer raised the questions below:
Could we use the TPS68470 in Non-HDI board? Is any impact?
What is advantage for MIPI camera if we use v-sync feature?
Best regards,
Randy Chen
Part Number: TPS68470 Hi, Team,
I have a question for TPS68470.
Can TPS68470 control the output timing of VCM_OUT and I2C command? It takes 4.64 msec until the command is sent to the VCM Driver after VCM_OUT rises. A customer need min 12 msec before VCM_OUT…
Part Number: TPS68470 HI Sirs:
Our customer using TPS68470YFFR for CCM, schematic as below,
when they want to boot up world facing camera, CORE, VANA and S_RESETN are low level.
From datasheet 8.3.3.1,
" When SDA and SCL are routed to GPIO1 and GPIO2…