LMH6629: How does the layout example plan ?

Ben Huang1

Intellectual 705 points

Part Number: LMH6629

According to 10.2 Layout Example in the datasheet, the evaluation board is 4 layers stack up.

I would like to clearly identify the tracing and every layer before a board fabrication

Could you please help to confirm whether the following layer definition is correct or not?

L1 (top layer) : Signal route

L2 (mid layer 1) : GND Plane

L3 (mid layer2) : V+ Plane

L4 (bottom layer) : V- Plane

Any recommendation for layout technique not mentioned in the datasheet is also welcome

Thanks

Regards

Ben

over 4 years ago

0 Sima Jalaleddine over 4 years ago

TI__Mastermind 30605 points

Hello Ben,

Your layer definition is correct. Another layout technique not specifically mentioned in the datasheet, is to cutoff inner planes underneath the feedback/output pins of the amplifier on the signal layer (top layer). I am in the process of looking for the EVM design files; I can share the Gerber files once I find them.

Thank you,

Sima

0 Sima Jalaleddine over 4 years ago

TI__Mastermind 30605 points

Hello Ben,

Unfortunately, I could not find the Gerber Files for specifically the LMH6629EVM. But, I have attached the Gerber files for a generic eval board for 1GHz parts matching the same package as the LMH6629 (WSON-8). We would also be able to help review schematic/PCB design files.

2744.GerberNCdrills.zip

Thanks,

Sima

0 Ben Huang1 over 4 years ago in reply to Sima Jalaleddine

Intellectual 705 points

Hi Sima

Thanks for the effort !

I am going to check the file first and ask the additional question if required !

Regards

Ben

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LMH6629: How does the layout example plan ?