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OPA2325: OPA2325

Part Number: OPA2325
Other Parts Discussed in Thread: TINA-TI,

Dear Sir,

We are using OPA2325IDR in the signal condition circuit.

we are giving signal Input : 0 to 5 V DC and getting signal Output in between: 2.4 to 2.5 V DC, but the expected output should be : 0 to 3.3VDC.

Output is not reaching the maximum output voltage of 3.3 VDC in IC1?

IC2 is working perfectly alright and the schematic is the same.

I am very confused, how to resolve this issue.

Please verify and suggest a solution.


  • Hi Murthy,

    please post a schematic.


  • Murthy,

    There is nothing to verify since you forgot to attach your schematic showing supply voltage and configuration used.  Please use Insert->Image/File button at the bottom of the Reply window to attach Tina-TI circuit schematic file or image of your application since without it we cannot assist you.

  • Murthy,

    Other than OPA2325 output, VF1, not being able to swing closer than 10-20mV from either rail, for 0 to 5V input the circuit should give the output between 10mV to 3.3V - see below.  

    Since you claim that the identical circuit with IC2 works as expected, the most likely explanation for IC1 output being between 2.4V-2.5V is that in the first circuit you forgot to include 100ohm Riso resistor in series with 100nF capacitive load, CL, resulting in the output oscillating or IC1 is damaged.

    The circuit is stable and has plenty of phase margin with 100ohm Riso resistor - see below.

    But it has no phase margin without series output resistor resulting in oscillation, which would show while using DMM meter as its average DC voltage value of 2.4-2.5V

    Please check the output of the first circuit with a scope or swap the IC's to see whether the problem follows IC or stays with the PCB board.

    Murthy OPA2325.TSC

  • Dear Marek Lis,

    Thanks for your warm reply,

    Please let us know,
    What should be the range of gain margin and phase margin for stable operation?

    I have connected 100Ohm and 100nF (RC Filter before the signal is going to the microcontroller).

    I have replaced the IC with the new one, Still the results are the same, and the output of 100 Ohms is also Connected.


  • Hi Murthy,

    I think the pot at the input and the absence of input voltage filtering and supply voltage filtering is the issue here. As the OPA2325 is very fast, any load current change will cause a supply voltage fluctuation which is fedback to the input via the pot. Also, there probably is capacitive stray coupling from the output of OPAmp to the pot and by this to the input of OPAmp.

    I would suggest the following modifications:


    Add a supply voltage filter to the OPAmp consisting of a 22R resistor and 100nF/X7R cap. The resistor can vary between 4R7 and 22R. With a bit luck you can even omit this resistor. But have the 100nF there and have it mounted closest (!) to the OPAmp.

    Use a pot which is not too high ohmic. Something between 10k and 100k seems appropriate. Use a pot with a metal enclosure and connect the metal enclosure to 0V. Even only this simple measure might solve the issue as now the capacitive stray coupling is heavily minimized.

    In any case, I would mount C7=100nF/X7R. It also minimizes the effect of capacitive stray coupling by generating a zero ohm path for HF to signal ground. But its main purpose is to prevent the destabilizing feedback via the supply voltage. To be effective even when the wiper of pot is set to 100%, insert R5=1k.

    To prevent destruction of OPAmp, if the supply voltage is suddenly shorted and C7 is discharging into the input of OPA2325, the current limiting resistor R1=10k is added. And to keep the capacitive stray coupling minimal again, C8=100p is mounted.

    By the way, C8 cannot cause a too high input current, because if the supply voltage is shorted, a current of 5V / 22R = 227mA is flowing through R4, while 99.9% is running out of C1 but only 0.1% = 227µA out of C8.

    The second stage is omitted and the charge bucket filter is connected to the output of the one and only OPAmp. R2 and R3 form a voltage divider and give a load resistance of 1k51. Figures 29 and 30 of datasheet demonstrate that 1k51 is not too low.

    The source resistance of charge bucket filter is the parallel resistance of R2 and R3, which is 338R and which is not too far away from your 100R. The slight increase should not be an issue.

    C2 could also cause a dangerous current flow into the output when the supply voltage is suddenly shorted. But R2=510R limtis the current to below 3.3V / 510R = 6.5mA.

    Keep in mind that despite the above filtering measures a clean, stable and noisefree supply voltage is still necessary.

    As you might have noticed, the scheme above shows the simulation circuit for the phase stability analysis. To translate it into a running circuit, connect "-IN" with "(-IN)" and "+IN" with "(+IN)" and remove the circuitry arround "VG1" and "VM1" at the bottom left.

    The circuit should work now. Keep in mind, though, that the buffer, the charge bucket filter and the ADC input should be located close together. And this is especially true for the pot at the input!

    To answer your question referring to the required minimum phase margin of a OPAmp circuit: As a rule of thumb, the phase margin should be higher than 45°. But it's wise to increase the phase margin to much higher values, especially if the circuit is "open", or by other words, when the input and/or output is connected to the outer world and/or cabling is involved. A phase margin of 45° might cause failing, if the circuit has to struggle with external EMI.

    The above circuit has a phase margin of 77° and should work properly.