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Direction of OP AMPS input bias/offset current

Gabriel Xu
Intellectual 2145 points

Part Number: TLV9062

Hi Team

Few questions about OP AMPS input bias/offset current:

  1.  Base on my understanding, the input bias current is base current of input transistor so the bias current direction should be the same for negative and position input? Is that right? For NPN input transistor input stage it should be flow input the OP AMPS like below diagram. Please correct me if I am wrong.
  2. If the bias current only have one direction,why in datasheet spec will have both positive and negative value?
  3. The bias current will have certain level mismatch, for example the IB+=160nA and IB-=120nA, so what's the definition of "bias current" in datasheet? My understanding is Ib=(160+120)/2=140nA.
  4. The offset current in such condition should be Ios=160nA-120nA=40nA?

  • 0
    TI__Intellectual 2145 points

    Few more questions about TI precision lab.

    training.ti.com/.../1100-L - Vos and Ib - Lab - slides_0.pdf

    In input bias/offset current section the calculation equation is shown below, my questions is:

    1. Why the Vib=Req*ib+Rin*ib? Rather than Vib*ib-Rin*ib? The Req majorly present the voltage in negative input.
    2. Why Req=R1//Rf?
    3. Should we make Rin=Req=R1//RF to minimize the input current effect? How to calculate the Vib in such configuration?

  • 0
    Guru 325800 points

    1. For opamps with BJT inputs, the bias current indeed is the base current.

    2. BJT opamps with rail-to-rail inputs are likely to have both NPN and PNP transistors; the total current might be positive or negative. CMOS opamp inputs do not need any DC input current for operation; the input bias current is leakage current from the MOSFET gate(s) and the ESD protection diodes; this also might go in either direction.

    3. There is one bias current for each input pin.

    4. Yes, the offset current is the difference of the two bias currents.

    1. The current flows through both resistors, in the same direction.

    2. Req is the effective resistance through which the input bias current flows. From the point of view of the input pin, R1 and Rf are in parallel.

    3. If we assume that the offset current is zero, then the effective resistances at both inputs should be the same, so that the voltage drop (caused by the bias current) over both resistances is the same, so that both inputs see the same error voltage, so that it cancels out. You do not calculate Vib; you just ensure that the resistances are the same. (If the offset current is not zero, you have to calibrate it and adjust the resistor. But in practice, if you care, you just use an opamp with low bias current.)

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 2145 points

    Hi Clemens

    Thanks for your reply. It's very helpful.

    Still not fully understand the input bias current definition. Take NPN transistor type input stage as example.

    The base current of each transistor can't be perferly match so the actual base current flow into each transistor should be similar level but not exactly the same. Like  IB+=140nA and IB-=160nA. What's the bias current and offset currnet in such condition?

  • 0 in reply to Gabriel Xu
    Guru 325800 points

    The bias current is 140 nA and 160 nA. The offset current is 20 nA.

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 2145 points

    Clemens

    But in datasheet only one bias current spec would be given, how the Ibias spec calculated from each base current?

  • 0 in reply to Gabriel Xu
    TI__Guru**** 174476 points

    Gabriel,

    In your example for one sample, there are two data points for IIB, 140nA , 160nA. There is one data point for IIO, 20nA 

  • 0 in reply to Gabriel Xu
    Guru 325800 points

    The datasheet specifies a typical value and/or limits. Each bias current value is expected to be near the typical value. Each bias current value is guaranteed to be inside the limits.