TLV4041: Latchable Comparator

Rohit 

Thanks for your post. Can you elaborate a bit more on exactly what is needed? You mentioned over current application, so does that mean you want the comparator output to remain in a logic high or low stated once the event is detected? Does it matter if the output l latches high or low or is the application flexible? Also, how would the latched condition be cleared? Is the system power cycled or does an external device such as MCU clear the latched condition?

chuck

Exactly i need is to detect Short Circuit in 72v/45AH Battery Pack Based on Mosfets as a power switch.(BMS).

So lets assume a shunt of 1mohm is connected in series of a Battery Pack at low side , now assume a Comparator is connected across Shunt with V+ Terminal with a Reference of 100mv at its Pin and V- Pin of a comparator at Shunt -ve end .

Here when ever a voltage drop exceeding 100mv occurs at -ve end of a shunt,V- gets > V+ and comparator output will toggle from High to Low. And Here Same State needs to be Latched once Output Gets Low from High State, until Controller do not latches. Here you can propose any logic as you prefer.

Same Signal i want to utilise to turn my Mosfets OFF from ON State. This switching will be faster than AFE Providing Action of 300 Micro Seconds.

Since 300 Micro Seconds Duration is Too High For Mosfetsto Sustain.

So Am looking at Comparator to assit within 1 -10 Micro Secs. during Short curcuit event.

Rohit

I am sure this will need some tweaking but this is what I am thinking (see attached TINA file).

By using a large amount of hysteresis, I can create a comparator output that latches, even if the current reduces to 0.

I used a 2m ohm shunt since TLV4041R2 has a 0.2V reference.  So the comparator output will latch high when the current reaches approximately 105A.

Not sure if that was what you were thinking, but we can scale rshunt and short circuit current accordingly.

The NMOS switch (I just used a random NMOS from the library) is how we clear the latch with an MCU.  When the NMOS is driven low (GND), the circuit works as expected and latches when the short circuit current level is achieved.  The latching effect is cleared when the NMOS is driven high, pulling the comparator input low.

ChuckTLV4041R2_OC_latch.TSC

Yes, it's correct what u have understand and implemented. 

Can you share what will be the response time for opam out put change, once v+  detected > 0.2 volt @ V-? 

Also will any noise affect , while I put opam in actual practical circuitry? Because once I faced it. 

Also this opam inverting terminal is having vref of 0.2 volts, can you suggest any opam whose non inverting terminal is vref?

It will help me to handle with less circuitry, else I need to convert non short circuit scenario after inverting opam output. Which will add one inverter. 

Thanks