Hello TI team,
I am working on the design of a board to measure tensions, from low voltages to high ones. This board includes the AMC3330DWER. I try to understand the layout recommended in your datasheet, but the fact of passing critical signals under capacitors C4, C5, as well as under C8, C9 is counterintuitive for me since it is possible to induce noise over the tracks, even being in differential mode. Is it not better to pass the critical signals over the bottom layer? Can you please explain the reasons for this kind of layout?
Thank you!!