OPA4202: OPA4202 Apply for an instrumentation amplifier

Hi Alvin,

what does not work with the circuit? What disfunction do you observe?

The schematic is incomplete. Please add the missing component values.

What is the common mode input voltage of your application? Are you violating the common mode input voltage range of OPA4202? Are you staying at least 1.5V away from the supply voltage rails?

Why are you connecting the cap of kickback filter directly to the output of OPAmp, without inserting the usual isolation resistor? What ADC do you use? What charge kickback filter the datasheet of ADC is recommending?

The OPA4202 is rather slow and shows a huge settling time of 30µs. This might be too slow for adequately driving your ADC input.

Kai

Hi Alvin,

I agree with Kai's questions here; the OPA4202 can work but there are many differences between the OPA324, and we don't have enough information to pinpoint exactly what it would be.  The common mode voltage range is definitely the first thing to check.  The OPA324 can work with the common mode input voltage down to the negative supply:

But, the OPA needs at least 1.5 V from the negative rail to be within the correct common mode voltage range - :

Hopefully this helps narrow it down.  To give any more details on what could be different, we'll need more information as Kai asked above.

Best Regards,
Mike

Hi，Mike，

Thanks for your reply.

I attached the picture with all component value.

We apply this circuit on the current acquisition circuit，and we test the voltage is that V1+=0V,V1-=-5mV.

What the "circuit cant work normally" means that the pin8(C output) is always zero ，not 257.5mV.

At the beginning, we suspected that our connection method affected the internal work of the IC, but other ICs could output normally, but Vos could not meet our requirements.

By the way ，can the output of OPAmp not be directly connected to the capacitor? What will be the impact?

The settling time of 30µs is only at the moment of booting, right? This won't affect us.

Thanks again.

Hi Alvin,

the impact of omitting the isolation resistor between the OPAmp output and the charge kickback filter capacitance is instability:

alvin_opa4202.TSC

The phase margin is only 9°. So your circuit is instable and does not work properly.

And the settling time is relevant during the sampling time, everytime the ADC samples the input signal. How much, depends on the ADC. Again, what ADC do you use?

Kai 

An isolation resistor of only 33R would be enough to increase the phase margin to a sane level:

Kai 

Hi Alvin,

I agree with Kai, you should definitely not drive a large capacitive load directly.  While this part does have great cap. load drive, it will be close to unstable with 0.1 uF.  See the plot below in the data sheet, at 25 nF, there is already 50% overshoot in unity gain, this is very low phase margin:

This must be corrected, but it may not be the only issue.  I did test this myself in a TINA simulation and it worked as expected (albeit with low phase margin).  It seems there must be something more with the configuration than the design itself.  Here are a few other questions I'd like to understand:

- Are you saying the measured voltage at pin 8 is zero volts, meaning, 0.000 V?  The most likely answer for this is that somehow pin 8 has been shorted to ground.  What is the actual voltage at pin 8 if that is not the case?

- Are the voltage sources used for the input grounded at the same potential as the supply voltages? What is the equipment used for the input voltage?

Best Regards,
Mike