OPA855: Phase error in Pspice model

Hi Renen,

try to decrease the amplitude of stimulating signal.

Kai

Hello Renan,

  That is a very good method to determine the origin of the issue. Agreed with above, the symbol does look different compared to the one available on the OPA855 folder. Otherwise, that is correct, the model and the datasheet differ by 180 degrees in phase, but follow the same trend. Usually, it is best to look at phase at 0-1kHz, then check the phase at the crossover to determine the phase shift/phase margin. 

   Here is the thread that confirms the discrepancy between the datasheet and the model. Michael's method of rotating the meter does fix the issue as shown below: 

Thank you,

Sima

Hello Sima,

Good day and thank you for this response. Here are some additional results from my customer:

1 - Hi Kai, I reduced the input AC voltage to 0.1 nV so subtract 200dBV in the gain plot to get the value you expect.
2 - Hi Michael, I did pick up on one of your previous posts that the phase margin was directly reported on TINA so I was not worried about these results from the TINA sim.
I created a separate OPA855 symbol that only has the pins covered by the PSPICE model. TI seems to only have OPA855 in a model that includes the "power down" and "feedback" pin, so I did find it odd that it was not included in the PSPICE model.
From my limited knowledge, KiCAd Eeschema uses ngspice (ngspice.sourceforge.net/ngspice-eeschema.html). As noted at the top of that page, the simulator can (and was in my case was) made compatible with PSpice and LTSpice.

3 - Hi Sima, my confusion came from the PSpice model. How can the output phase lead the input phase by 90deg? It should start at 0deg in and decay in an Aol plot as there are no zeros, right?
I also plotted the from 1uHz to 10GHz to show nothing is happening at lower frequencies (see picture attached).

Just in general, Eeschema needs you to choose which pins are simulated and you can note the order of the pins set out in the PSpice model and set them as shown in the attachment.

Attachments.zip

Regards,

Renan

Hello Renan,

  Correct, the OPA855 does have a feedback pin and power-down pin, while the model does not include these pins. The feedback pin (pin 1) is internally connected to the output of the amplifier (pin 6) to simply high speed PCB layout in order to minimize parasitic inductance and capacitance to these critical pins. Unfortunately, the power-down functionality for the device was not modeled. For more information on device in power-down mode, please look at OPA855 datasheet figures 7-23, 7-24, 9-8, and 9-9. 

   I see, the confusion lies in open-loop vs closed-loop analysis. For open-loop, you are looking at the loop-gain crossover where noise gain intersects the open-loop gain of the amplifier to find the stability or phase margin of the system. The high value capacitance and inductance are there to break the loop between input and output, but also converge in simulation. Simulations require a path to DC for convergence. Michael's suggestion at breaking the loop at the input is most accurate to account the open loop output impedance of the amplifier + feedback load. 

   Understood, thank you for the explanation on the Eeschema software. 

  Thank you,

Sima 

Hi Michael and Sima,

I believe the following simulation addresses Michael's concerns and breaks the loop at the input. Here we see that the KiCad (Eeschema) simulation still shows that V(out) has an incorrect phase lead.

I chose VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω from to follow the testing parameters in the datasheet for OPA855.

Please let me know if you have any thoughts on how to resolve this issue.

Regards,

Renan

Hello Renan,

  Sorry for the confusion, it was just a note for in the future stability simulations. That is correct, breaking the loop a different way won't change the results much. In most cases, it can be more accurate. This type of simulation will provide you overall stability of the amplifier + its configuration. The phase margin does tell us how close to complete phase inversion (-180 degrees), and thus instability. So, it is already quantifying the phase lag of the output relative to its input.

  The easiest way to view phase lag/lead by signal (pictorially) rather than relative numerical value would be to close the loop, and view the transient input and output signal.  

Thank you,
Sima 

Hello Sima,

Sorry, I meant to include this simulation in my last post to address Michael's concerns.

On a different note, I am still concerned about the discrepancy between the result of the PSpice model and the TINA model as at this point I am not trying to simulate the closed-loop behaviour.
In the PSPICE model, the increase in phase from ~5 degrees at 100kHz to ~85 degrees at 10MHz does not seem physical to me while the decrease from ~-5 at 100kHz to ~-85 degrees at 10 MHz in the TINA model seems to make sense and agrees with the OPA855 Figure 7-10 Aol plot.

Is this an issue with the PSPICE model or am I missing something?

Regards,

Renan

Hello Renan,

  Thank you, the images helped. That does seem strange that the PSpice Vout phase increases to 90 degrees, while Tina's Vout phase decreases to 90 degrees. 

  I will look into this issue, and get back to you shortly.

Thank you,

Sima 

Hello Renan,

  Thank you for your patience. I tried both PSpice models (including OPA855 Unencrypted PSpice Model Package Rev D), and it produced the same results on PSpice. I wasn't sure how to switch polarity of the meter in PSpice, but the phase here decreases by 90 degrees. 

   Maybe there is an issue during insertion of the PSpice model into KiCad. I am not familiar with this software, but I found a guide that might be helpful. I would recommend the customer redo the process of inserting the netlist into the software.

OPA855_Stability-PSpiceFiles.zip

Thank you,
Sima