• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 48 subscribers
  • Views 1684 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV3501 input-output isolation

rfengr
Intellectual 720 points
Other Parts Discussed in Thread: TLV3501

Hello all, 

Basically, I had lots of issues with the output ringing due to the fast response of the TLV3501, but I fixed that by increasing hysteresis and the use of the 1K-ohm output resistor.

The problem now is somewhat strange to me, and I think there is some sort of isolation issue between input and output. When the reference is set around midway around the pulse amplitude, the input signal is (...insert unknown word description ..), I guess replicated, delayed, or jitter-in the time domain ?

I've included a picture of what I'm talking about, look how the green-signal initially has a single peak before applying the reference (left picture) and then gets another peak when the reference voltage is applied/adjusted (right picture). The other two peaks are also effected similarly, but not shown in the snapped picture. When you run the oscilloscope continuously, you notice that the green signal is jittery, as well as the output. I need a clean output result for my application.

Possible concerns/questions I have:

1) The problem was slightly improved using Cbp1 and Rload.

2) How can I isolate the rising/falling edge of the comparator from the input ?

3) Rout improves the situation, but increasing it further will increase the output "falling-time"

Any suggestions ?

Thanks

  • 0
    Intellectual 720 points

    Quick correction: The Green-signal is actually taken after Cbp1, or at the IN- of the comparator, which makes much more sense because the mid-rail voltage is bypassed.

  • 0 in reply to rfengr
    Intellectual 720 points

    Quick explanation of the circuit:

    1) I have a 6MHz input signal that has three pulses.

    2) Input signal is rectified and an envelope detector (diodes + low pass filter) detects these three pulses. 

    3) The DC factor of the output of the envelope is bypassed with Cbp1, and into Rload and the comparator input. 

    4) Circuit Application: Detect the time difference between the three pulses.

     

    Here are some worse pictures:

    Hope this gives you a better picture of how the input signal jitters when the reference voltage (purple-graph) is applied to the input signal (green-graph).

  • 0 in reply to rfengr
    TI__Guru* 93105 points

    Hello rfeng,

    I suspect the source of the problem is what you described; an issue with the TLV3501 loading the passive network preceding its input. The TLV3501 input bias, although low under DC conditions, will increase as the input rapidly slews. I am speculating that the increased input current causes loading of the high impedance passive network connected before the comparator input. The voltage folds back causing the comparator output to switch to a false state as the input threshold is inadvertently crossed. Apparently the effect takes place as you move Vref off the midpoint. You may find that a somewhat slower, very low input current comparator corrects the problem.

    Also, I don't know your circuit constraints but I suspect scaling the passive components, reducing resistors and increasing capacitor values by the same factor, may help. Doing so would lower the impedance of network and increase the transient current capability. There may be a way to add an active buffer, but that would increase the circuit complexity and cost.

    I hope this helps.

    Regards, Thomas

    PA-Linear Applications Engineering

  • 0 in reply to Thomas Kuehl
    Intellectual 720 points

    Thanks for the reply Thomas,

    As I mentioned earlier, it seams that increasing the output series resistor Rout improves the situation considerably. This, however, has the adverse impact of increased falling/rising time at the output, but nonetheless, solves the problem! However, I'm left wondering, what is the use of a fast comparator if you can only use it in the slow mode.. there must be another way because this solution seams to be counter productive.

    If what you said is right about the comparator input being loaded, then what would you recommend we do with Rload (increase/decrease)  ? I guess, your suggesting to decrease it. I remember I needed Rload because the signal seamed to be floating without it, which made me guess that the input impedance of the comparator was too high. If the input impedance is too high, then its a mystery why the input is being loaded.I suspect its the fast transient response as well .. :(

    Increase capacitance while reducing resistance, will increase input current to the comparator, but that will cause increased voltage drop across the diodes which is not desirable for this circuit because the VDD is 3V coin battery, and I would like the circuit to also work at reduced voltages down to about 2.3v.

    I will try 10K ohm Rload, and let you know what happens.

    Thanks!

     

  • 0 in reply to rfengr
    Intellectual 720 points

    Reducing Rload to 10K made things worse. Actually increasing it twice the value (200K) seams to be the same as (100K).

    I changed Rout to 2K, it solves the problem, but my rise-time = fall time = 130ns :(

    I would appreciate it if anyone has a better solution than increasing Rout to 2K-ohm.

    THanks

     

  • 0 in reply to rfengr
    Guru 21975 points

    rfengr,

    You say that increasing Rout seems to make a dramatic improvement. Increasing Rout would appear to reduce the transient current that the comparator must supply to charge (or, in this case, discharge) Cout. I'm not sure if Cout is installed or perhaps this is just accounting for stray or wiring capacitance.

    Anyway, the fact that this current transient is causing a problem suggests that there may be a ground bounce issue. The low -going output edge causes a current pulse to flow into the comparator's output terminal and out its ground terminal. Consider where this current then must flow. It should have a direct, low inductance ground path back to ground side of Cout. Check out this aspect of your board layout. Also, check to see that your layout minimizes the influence that this current pulse has on the input signal and reference voltage on the + input. For example, a ground bounce on the low side of the bypass capacitors on Vref would create a bounce at the + input of the comparator.

    Also, try adding some additional bypass cap (0.1uF ceramic) directly across its supply pins and see if it helps.

    Regards, Bruce.

  • 0 in reply to Bruce Trump
    Intellectual 720 points

    Thank you Bruce,

    I've added a whole bunch of bypass capacitors in parallel including the 0.1uF and they are all located next to the chip, but same problem.

    I read a little more on ground bounce, and I guess it is different than voltage dips I'm more familiar with due to large current pulses (mostly noticeable in battery operated boards-due to limited output current supply of the battery), which is what the bypass capacitors are suppose to take care of. However, it seams that "ground bounce" is mostly caused by inductance in the trace path.

    I think you might have a valid point, but I can't easily modify the traces on the fabricated PCB though. I have included the PCB schematic showing the + and - path to the capacitor.

    Note: the output capacitor is NOT populated (open), but the 10x oscilloscope-probe has I think a 2pF input capacitance, and the actual load is a schmitt-trigger input of 5pF, and then adding some 3pF stray PCB capacitance, it might be about 10pF total.

    I guess I never considered the inductance of the 10x osc.probe ?

    In any case, I think we all seam to agree that the fast rising/falling edges of the output causes large current pulses that are causing the signal bounce on the input.

    Lessons learned:

    1) 0.1uF, 1nF, and 100pF bypass capacitors on both VDD and VREF for fast changing currents

    2) choosing a slower comparator might help improve things since output transients are slower

    3) reduce ground and supply paths from (input, output, and supply) to chip GND in order to reduce GND-bounce

     

    Hope this might help others ... and thank you so much for all your inputs !

     

  • 0 in reply to rfengr
    Intellectual 720 points

    since the output capacitor Cout is not implemented, I'm not really sure why I included that previous picture... oh well

  • 0 in reply to rfengr
    Prodigy 110 points

    Hey rfengr,

    As for the Rout and Cout, I think the 130ns rising or falling time is expectable. Considering the 4RC as the rough rising time, your Rout=2K, Cout depends. My scope detector Cout is 13pF, plus 2pF from PCB, so your rising time is 4*2*(10^3)*15*(10^12)=120ns, this is what u saw in scope, but it doesn't mean the real rising time in ur real circuitry. Therefore, in order to decrease the rising time, u have to either reduce Rout or Cout.

    BTW, are you adding Rout to minimize the feedback line effect?

    Lian