TLV9062: Shutdown vs power-off

I looked at the recently updated application note sboa367 concerning the shutdown function of the TLV90xxs devices. I'd like to understand the tradeoff between shutdown and simply powering the chip off at pin V+. For example, a 3V3 design might use the amplifier to drive an ADC for a short time -- say 100 ms -- at a rate of 1 second. I could gate it on and off using shutdown while leaving it connected to 3V3. Alternatively, a 3V3 gate pulse could be applied at V+ followed by an appropriate time delay to let any transients/glitches settle before enabling the ADC. The 100 nF bypass capacitor on V+ would have to charge each cycle, but the current consumed (330 nA) would be commensurate with the quiescent current in shutdown (500 nA). In this example, I don't see the benefit of having shutdown but perhaps I am missing something?