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XTR111 - Dynamic Performance question

Other Parts Discussed in Thread: XTR111

On page 15 of the datasheet there is a description of Dynamic Performance.  In the second paragraph there is a reference to settling to full resolution .. around 100us. 

Is the high frequency noise only present during a step change or is it there all the time? 

We have a 0.1uF capacitor on the output of our V to I.  Would that improve the dynamic performance?

 

Thanks

Dave

 

  • Hello Dave,

    Thanks for your question on the XTR111.

    The high-frequency noise is present at all times because of how the XTR111 uses multiple internal current sources to regulate the total output current .

    The 100nF capacitor placed at the output will greatly reduce the output noise. Measurements I took in February showed an AC noise magnitude of 13.47mVpp with an output capacitor of 94nF (2*47nF). Of course, the slew rate will be impacted by the extra output capacitance as well, and the 94nF value in particular resulted in a 123us slew from 10%-90%. I have attached that report to this post for your reference.

    Best regards,

    Ian Williams
    Linear Applications Engineer
    High Performance Linear

    XTR111 Follow-up Noise and Slew Rate Testing.ppt
  • Dear Dave,

    I am using XTR111 as output stage of my device, as a voltage to current converter as well as voltage to voltage converter.

    I am facing the problem of unexpected noise at output in current converter and in voltage to voltage converter, output has additional oscillations.

    Details are as follows:

                        Config.               I/P                            O/P

           1)          V - I                   0.2V                      0.2 Vdc + 10mVpp noise                                         * O/P Terminated with 500 ohms

                         V - I                   10V                      10 Vdc + 80 mVpp noise                                          * O/P Terminated with 500 ohms

     

          2)            V - V                  10V                     10 Vdc + 0.2 Vpp Oscillations @ 100KHz             * O/P Terminated with 500 ohms

     

    If we connect 1 uF capacitor across O/P terminals then all the above mentioned problems are reduced to acceptable levels.

    However, my application prohibits use of O/P capacitance more than 10nF.

    Circuit has been used as per the sample designs given in your application notes.

    Please advice on the above.

    Regards,

    Kabir

  • Hello Kabir,

    Would you please share a schematic for this design?  It sounds like you may have an instability issue in your system which we need the schematic to help diagnose.

    Please accurately show where the input and output measurements are being taken from on your schematic as well.

    Thank you!
    Collin Wells
    Precision Analog