PGA281: PGA281

Hi Hale,

First off, it will take some current to charge the bypass caps. For example, in order to charge 10uF up to 10 V in 1 ms, it will require 100 mA if it was constant current charging.  So, 60-70 mA may be reasonable.  Can you slow down the ramp rate to reduce the inrush current?

Also, the PGA281 EVM board has jumper options for the VSOP rail; can you verify you connected the jumper option (JMP1) for "External VSOP"?    You will get excessive currents if you attempt to drive the LDO output.

Also, on your second scope plot, it looks like the output voltage is ~8V - the output voltage should be limited by the voltage on VSOP, and, if VSP was not powered, I don't know how 8V could be created.  Can you also measure the voltage at VSP during that time?

Best Regards,
Mike

Thanks for your reply. 

First,   circuit design is complete. I connect VSOP to 5V supply with magnetic beads. So it's hard to redesign the schematic. As for  bypass caps, you mean capacitor on the EVM or capacitor integrated into the chip or else？

Second, I'm sure that I connected the jumper option (JMP1) for "External VSOP". 

Thirdly, on my second scope plot, I had some problems with my previous test. And I tested it again, as shown in figure.

                                VOP-GND                                                              VON-GND                                                              

Why did VOP and VON (blue) have a step? And would it be clamped to supply voltage or angthing?

Thanks for your reply. On my previous second scope plot, I had some problems with my previous test.

And I tested it again, as shown in figure.(yellow and green is in+ and in-)

VON-GND       VON(blue)    VSP(purple)  

VOP-GND      VON (blue)      VSP(purple)                                              

So why did VOP(blue)  and VON (blue) have a step? And would it be clamped to supply voltage or anything?

I tested PGA821 (VSOP power up before VSP)  before and caused PGA281 output range over ADC input range(5V).

Hi Hale,

As mentioned in the power supply section of the datasheet (see Luis's comment above), it is safe to power on VSOP before VSP. However, when VSOP is powered and VSP is not, the device is not in a state of linear operation. It is normal to see some shift at the output as the supplies are powered on and the device settles. This voltage shift at the output will always be within the VSOP-VSON supply range, unless the node is being overdriven by some other source.

The scope captures below show the output behavior as the PGA281EVM power supplies are turned on. Notice that the output never exceeds VSOP rail.

Also, your scope shot seems to show some oscillation on your power supply. Can you provide a picture of your EVM set up?

Regards,

Zach

Hi, Zach. Thanks for your reply. You made it very clear. But I still have some question.

Q1. As for second picture, could you show me VOP-GND and VON-GND waveform when VSP rise?

Q2.As for your words 'It is normal to see some shift at the output as the supplies are powered on and the device settles', could you explain how the shift generated and how to avoid it or reduce it. The second picture shows that VOP-VON has reached 5V which is too large for subsequent ADC inputs(about 3V) and leads device to be locked.

Hi Hale,

The voltage shift at the output is due to headroom and common-mode violations as the device powers up. As the VSP/VSN supplies are ramped, the input stage becomes biased and will begin to amplify the input signal. However, until the common-mode and headroom requirements are satisfied (see power supply section of datasheet), the device is in a non-linear state and the output will collapse to the output stage power supply rail. Once the power supply requirements are met, the device will operate linearly as shown in the previous scope capture.

In your initial post you stated that you are expecting up to 3.8V at the output (VOP) with a VOCM of 2.5V. Can you confirm what is your expected input and output signal? What is the power supply of the ADC you are driving? Can you specify the ADC and provide a schematic for clarification?

Do you have 3V supply available? If you want to limit the output voltage <3V in all cases, you may use 3V supply for VSOP. The output voltage cannot exceed the power supply.

See below VOP-GND and VON-GND do not exceed VSOP as VSP is ramped.

Regards,

Zach

1. Ok, I get it. One more question，why this 2 picture seems diffierent，when VSP is rising. In the first picture，VOP-VON equals 5V，in the second picture，VOP-VON is changing.

Hale,

When I set up the EVM for the second image I used a DC signal source for the input. The first image shows AC signal source. Additionally, on the first image I am showing differential VOP-VON on a single oscilloscope channel whereas the second image shows VOP-GND and VON-GND on two separate channels.

Sorry for the confusion, in either case the output cannot exceed VSOP.

Regards,

Zach

Hi, Zach! I still have 2 question.

Q1. My customer wants to give 2.6V to IN-N and 5.2V to IN-P, gain=1(G4:G0=00011), VOCM=1.65V, and wanted to get 0.35V ~2.95 on VON and VOP, with VSP=15V, VSN=-15V, VSOP=VDD=5V. If VSOP power up before VSP will cause PGA281 output range attach 5V, it's over ADC input range(3.3V).

And as you said, 'the output cannot exceed VSOP', is it feasible to reduce VSOP=VDD=3.3V? My customer said that VSOP=VDD=3.3V didn't give enough headroom for VOP. And distortion will occur.

Q2.As you said 'The voltage shift at the output is due to headroom and common-mode violations as the device powers up', can you explain the relationship of VSP and VOP? And why the headroom is supplied by VSP, not VSOP, or by both? Or give me more details about the cause of voltage shift.

Thanks so much!

Hi Hale,

The PGA281 can swing (worst case) 100mV from the VSOP supply rail. Lowering VSOP=VDD to 3.3V will provide plenty of headroom for VOP if the maximum output signal is 2.95V. 

If you are seeing distortion in this case, it is not the voltage output swing of the PGA281 that is causing the issue. Without seeing the schematic or knowing which ADC is being driven, I cannot provide much insight into why the customer is seeing distortion. Depending on the type of ADC, the sample rate, and the resolution, PGA281 may require an additional buffer to drive the ADC due to its complex output impedance over frequency.

Can you provide a schematic? Can you specify what ADC are you driving? What is the sample rate and resolution?

As for the power supplies, The PGA281 is an instrumentation amplifier with a high-voltage front-end amplifier stage and a low-voltage output amplifier stage. The high-voltage input stage power supply (VSP/VSN) allows for input signals with a large common-mode voltage to be level-shifted down to a voltage supply range that accommodates sampling with an ADC (VSOP/VSON). The front-end stage and the output stage each have their own common-mode and output swing specifications that must be met to ensure linear operation of the device. The headroom of the output stage is determined by the output power supplies (VSOP/VSON), however you cannot expect linear operation at the output stage when VSP is powered down and therefore there is not linear operation at the input stage. You must follow the datasheet specifications for both power supplies in order for the device to operate linearly. During startup, as the power supplies are ramping up, the device will not behave linearly until these specifications are met.

If you would like a detailed explanation of input/output limitation and non-linear behavior in op-amps, you may refer to the following TI Precision Labs training videos linked below. These, and other Precision Labs videos, are a great reference for everything op-amps.

https://training.ti.com/ti-precision-labs-op-amps-input-and-output-limitations-non-linear-behavior?context=1139747-1139745-14685-1138798-13960

https://training.ti.com/ti-precision-labs-op-amps-input-and-output-limitations-common-mode-voltage?context=1139747-1139745-14685-1138798-605540

https://training.ti.com/ti-precision-labs-op-amps-input-and-output-limitations-output-swing?context=1139747-1139745-14685-1138798-605541 

Regards,

Zach

Hi, Zach! I want ta ask why VSP power up before VSOP supply will cause large VSOP current about(60~70mA).

Why VSOP power up before VSP supply will not cause large VSOP current about(60~70mA), as I asked the same question first time?

Hi Hale,

Are you seeing this current spike on the PGA281EVM, or only on your custom board? Or does it occur on both boards?

VSP/VSN and VSOP are separate power supplies and turning on one supply should not force current through the other supply.

See below for PGA281EVM as I power on VSP/VSN, the voltage and current of VSOP is not affected. 

Can you provide a scope image showing the voltages of VSP, VSN, and VSOP while the VSOP current spikes?

Please also include an image of your bench setup.

If this current spike occurs on your custom board but not the PGA281EVM, I will need to see a schematic of your custom board in order to further support this issue. If you do not want to post your schematic on the public forum you may send me the schematic directly over email.

Please address the following so that I may better support this issue:

1. Are you seeing this current spike on the PGA281EVM, or only on your custom board? Or does it occur on both boards?
2. Can you provide a scope image showing the voltages of VSP, VSN, and VSOP while the VSOP current spikes?
3. Please also include an image of your bench setup.

Regards,

Zach

If VSP power up before VSOP supply will cause large VSOP current about(60~70mA), as shown in figure.(yellow: IN-N; green: IN-P; pink: VSOP current; blue: VOP-VON). A lot of PGA281 power up at the same time will cause VSOP supply source current protection. And it occurs on both boards when VSOP is powering up and VSP has powered up before VSOP supply.

Hi Hale,

I understand you are seeing your VSOP supply spiking 60~70mA of current when VSOP is ramping up and the VSP supply is on. Additionally, you see this behavior on the EVM as well as your own custom board. Thank you for the clarification.

Using the PGA281EVM, I measured VSOP current as VSOP is ramped with VSP/VSN powered on. See below.

There is some current spike (~4mA) but I cannot replicate the 60~70mA behavior you are describing.

Can you provide a scope image showing the voltages of VSP, VSN, and VSOP while VSOP is ramping up and the current spikes?

Can you provide an image of your bench setup?

I will need to see the voltages of all the power supplies during the fault condition, as well as the bench setup in order to help with debug.

Thanks,

Zach

ok, I will show you later.

As for your picture, I want to know about IN-N and  IN-P voltage. Could you please tell me this information, because I use 2.6V IN-N and 5.2V IN-P, Vocm 1.65V.

Hi Hale,

For this test I used IN-P = 1Vpp sinusoid, IN-N = GND, VOCM = 2.5V.

Are you using an external voltage source to set VOCM to 1.65V? If so, are you powering on VOCM before or after VSOP?

There are internal ESD diodes between the VOCM and VSOP pins. If VSOP begins to ramp when VOCM is already powered to 1.65V, the internal ESD diodes will be forward biased and will conduct current until VSOP ramps to the cutoff voltage.

If you can, please also show scope image of the VOCM voltage when VSOP is ramping up and the current is spiked.

Thanks,

Zach

ok. I test it with VOCM=2.5V=VSOP/2, obtained by VSOP separation. 1.65V is customer choice.

Hi Hale,

I'm looking forward to your results. One more thing to consider, previously we talked about lowering VSOP from 5V to 3.3V as this will better suit your desired output range. In this case VOCM = VSOP/2 = 1.65V obtained by the R3,R4 resistor divider on the EVM.

Regards,

Zach