LF198QML: LF198 abnormal OUTPUT

Hi Woo,

you apply +5V to pin 8 before the LM198 is powered-up? Not good. Please also read footnote (3) of the "absolute maximum ratings" of datasheet.

You should follow the approach shown in section "logic input configurations" where the reference voltage is generated by the help of a voltage divider from the positive supply voltage. This approach prevents that the voltage at pin 8 exceeds the voltage at the positive supply voltage pin of LM198.

The same is true for pin 7. The voltage at this pin should also not exceed the supply voltages.

Also, you should not expect that the LM198 is already properly working before being powered-up or during the power-up phase. The "sampled" voltage in this period should not be expected to be valid.

Kai

Kai,

Thanks for assisting Woo by pointing out the proper power supply sequence and footnote 3 for the LF198QML.

Regards, Thomas

Precision Amplifiers Applications Engineering

Hi Kai/Thomas thank you for answer.

I agree with the content that it will behave abnormally by the incorrect power sequence. But i have a few additional questions.

Datasheet footnote(3) was understood as defininig the voltage level of the logic pin for proper logic operation and it seems that it is already designed normally in the captured circuit among the question above. (Logic Ref. = 2.5V)

And I don't understand how footnote(3) describe the sequence relationship between supply voltage and logic pin voltage.

Thanks.

Hi Woo,

footnote (3) says:

"Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the
supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply."

You should read between the lines:

The first sentence says that the input voltage on the logic pins can be equal to the supply voltages without causing damage. But they are not allowed to exceed the supply voltages.

The second sentence says that one of the logic pins must always be at least 2V below the positive supply. But how shall this work, if the positive supply voltage is down to 0V? Look at your scope plot.

Also, older datasheets of the LM198 or of clones of the LM198 show that an insane current will flow into the chip, if any of the input voltages exceed the supply voltages of LM198.

Kai

Hi kai thank you for your answer

As you can see from the above waveform, the power sequence is designed so that the voltage input to the logic pin starts about 1ms earlier than the supply voltage input. 

I have confirmed that this doesn't match the darasheet content of LF198 as you answered.

It will be good to change the power sequence normally, but the power sequence of +5V and +-15V cannot be changed due to the characteristics of the already applied DCDC converter.

You already given the answer 'insane current will flow into the chip' but isn't condition when the voltage of the logic pin exceed the supply voltage continously?

So what I want to check is whether it is critically affected by chip due to a power sequence that differs by about 1ms, please give your answer.

Please then check whether the chip should not be applied.

Currently, we need to apply LF198QML chip, but if there is an impact due to Power sequence, it could be a problem, so im asking.

Hi Woo,

to prevent the input voltage at pin 8 from exceeding the supply voltages of LM198 I wrote earlier?

I already wrote:

kai klaas69 said:

You should follow the approach shown in section "logic input configurations" where the reference voltage is generated by the help of a voltage divider from the positive supply voltage. This approach prevents that the voltage at pin 8 exceeds the voltage at the positive supply voltage pin of LM198.

And you can manage the signal at pin 7 in a similar way: Add a simple NPN transistor stage (inverter) with the collector supplied (via a resistor or resistor voltage divider) by the positive supply voltage of LM198. By this the voltage at pin 7 can never exceed the supply voltages of LM198.

Kai

Hi kai

Currently, the development stage of the equipment is completed, so it is not possible to apply the circuit addition or design change.

Therefore, I want to get an answer whether there is a possibility that the chip may be damaged when the chip is driven in the power sequence above.

The reason why I keep asking is that the current hardware development stage is over, so it is not possible to make additional improvements with circuits. So, it was confirmed that pin 7 where 5v is input is dropped to 0v with software and it works normally.
However, as in the above waveform, I am asking if there is no problem even if I continuously take the initial abnormal operation caused by the wrong power sequence.