Because of the Thanksgiving holiday in the U.S., TI E2E design support forum responses may be delayed the week of Nov. 21. Thank you for your patience.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

INA190: VREF input characteristics

Part Number: INA190
Other Parts Discussed in Thread: INA2191, INA191

Hi,

I have an application that uses 19 INA190A2 differential amplifiers and need to bias the VREF pins so that the amplifier output voltages keep the ADC in the linear range over the full-scale input current being monitored.

I would like to distribute a common voltage to all of the amplifier's VREF input pins but can not find any information on the VREF input characteristics.

I am pretty sure that this is a common application.

Does anyone out there have some information that could help?

Thank you,

David

  • Hello David,

    Looking into the REF pin for INA190A2 is 1MΩ + 400kΩ and into an internal bias voltage that is always set to Vs/3 (analog ground essentially). The 1MΩ resistor hangs off the non-inverting pin of 2nd stage amplifier and the 400kΩ is the resistance is the input resistance connecting 2nd stage IN+ to 1st stage output. Both resistors are precision matched to the the resistor network on the inverting side of the 2nd stage amplifier to create the difference amplifier. Both values can vary by +/-20%. Thus, Iref = (Vref - Vs/3)/(1.4MΩ) typically.

    Now all of this is irrelevant if you drive all 19 REF pins with a low output impedance voltage source, such as op amp buffer driving a reference voltage set from a resistor divider off Vs. This would be the ideal case. Your souce also would not need to drive/sink much current, probably in total ~19*2µA.

    However, as soon as your Vref source output impedance exceeds ~100Ω your going to add error including the absolute value of Vref. For example, with a high-Z source, you might want to set Vref to Vs/2, but due to Vref input impedance, the actual bias voltage of Vout will be Vs/2 +/- error and this can reduce the dynamic range of your circuit because you would have to account to a fluctuating bias point. You can read more about how to calculate this error with this application note:

    https://www.ti.com.cn/cn/lit/an/sboa551/sboa551.pdf

    Note that you can negate offset and gain error from high-Z Vref sources, by the ADC measuring the differential output (Vout with respect to Vref) as opposed to single-ended Vout.

    You can simulate the input behavior I describe above with the functionally equivalent INA2191 spice model available at link below. Unfortunately the INA190 spice model might not have this exact input characteristic behavior modeled, but the INA2191 definitely does (it even mentions it in the header of the model netlist). Sorry for the inconvenience. We are working on publishing a 2nd INA190 spice model to support this soon.

    https://www.ti.com/product/INA2191#design-tools-simulation

    Given that you have 19 circuits, you could consider using the INA2191 over the INA190 since the INA2191 is dual channel INA191 and the INA191 is essentially the INA190, but in a smaller package and slightly different enable voltage.

    Sincerely,

    Peter

  • Peter,

    Thank you for the detailed answer.  It was what I needed.  A dual channel version would not be optimal for my application.  I'll check out the INA191.

    Again, Thank you,

    David