This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PGA113: Is this schematic correct?

Part Number: PGA113
Other Parts Discussed in Thread: OPA325

Hi all.

I would like to use the PGA113 to set the first stage gain to the analog circuit on my sensor test board.

As you can see in the picture attached below, there are three different stages:

1) differential input stage

2) band-pass filter with two Sallen-Key stages

3) programmable amplier output stage

The supply VDDA_B is 3,3V. I got the VREF1 from VDDA_B with the resistive partitor R10-R11, so the VREF1 is equal to VDDA_B/2=1,65V.

In the PGA113 I only use one channel, so I put CH0 to GND with 1K resistor, as it was suggested from Luis in this discussion: PGA113: unused MUX pin termination.

I put VREF1 on pin 4 of PGA113 (pin VREF). Moreover the VREF1 voltage was applied to the differential input stage and to the first stage of band-pass filter.

I can't simulate the entire schematic, because I don't find the PGA113 spice model.

Do you think the schematic is correct?

Thank you.

Gabriele.

  • Hi Gabriele,

    I think the gain of input stage is too high. A gain of 1000V/V in combination with a 10MHz OPAmp provides a linearizing gain reserve of only 20dB at 1kHz. i would evenly split this huge gain onto two OPAmps.

    There's another issue: Pseudoground circuits often suffer from the fact that the pseudoground (VREF1) is no true ground, which means that it cannot absorb arbitrary ground currents and that the impedance is different from zero Ohm, especially at the higher frequencies. So, the common mode rejection of your differential input amplifier may suffer at higher frequencies. Some remedy is to mount a capacitance from the output U3002 to signal ground. But in this case U3002 would have to be phase lead compensated for the capacitive load, either by introducing a simple isolation resistor or by using the dual feedback method explained in this TI's training video series:

    https://training.ti.com/node/1138805

    Kai

  • Hi kai and thanks for your reply.

    One note I forget to say before is the amplitude of the input signal INA-INB. The amplitude is less than 30uV.

    I'll try to replay to your assertions.

    I think the gain of input stage is too high. A gain of 1000V/V in combination with a 10MHz OPAmp provides a linearizing gain reserve of only 20dB at 1kHz. i would evenly split this huge gain onto two OPAmps.

    As you can see in the picture attached below (from OPA325 datasheet), the BW is about 100kHz with G=100V/V. I think the BW is next to 10kHz with G=1000V/V. This BW is adequate for my application, because the information carried from the differential signal INA-INB is around 300-800Hz.

    There's another issue: Pseudoground circuits often suffer from the fact that the pseudoground (VREF1) is no true ground, which means that it cannot absorb arbitrary ground currents and that the impedance is different from zero Ohm, especially at the higher frequencies. So, the common mode rejection of your differential input amplifier may suffer at higher frequencies

    I think you're right.

    But, as I write above, the frequency range of interest is 300-800Hz. Infact I realize a differencial amplifier with low-pass filter and, after that, a band-pass filter to close the BW only in the range of my interest. So I don't think the performance degradation of CMRR was a problem to my application.

    What do you think about it?

    Gabriele.

  • Hi Gabriele,

    The PGA113 section of the circuit looks good.

    Your input gain and filter stages appear to provide your desired bandwidth based on 300Hz-800Hz input signal. 

    In addition to Kai's comments, I would add that your R10/R11 resistor divider is drawing 1.65mA. Increasing your resistor values up to 10kΩ will reduce this load on your power budget.

    Thanks,

    Zach