TLV9062: Cost optimized design for 4-20mA current loop measurement & CT measurement

Hi Shreeneet, 

Thanks for providing a lot of information about the system and required specs. Do you have any basic block diagram of what you are envisioning the circuit will look like? 

Best Regards, 

Robert Clifton 

Hello Robert,

We have explored several reference designs, but the presence of numerous discrete components in the circuits is not ideal for our requirements.

We received valuable guidance from @Art & @Raymond from the Precision OpAmp team, suggesting a solution. However, the cost of the  TLV333 OpAmp exceeds our budget for this particular use case.

As a result, we are considering using TLV9002 or TLV9062, but before finalizing the design, we would greatly appreciate feedback from the TI Community on these decisions.

Specifically, we seek input on the following points:

• How can we minimize errors in the unity gain configuration with a Voffset of 1.6mV?
  • Which Offset value should we consider, the typical (0,4mV) or the maximum (1.6mV) value as per the datasheet?
• How can we reduce the need for external components in the CT's secondary side measurement, where a gain up to 50 may be required without exceeding the error budget of 0.2-0.4%?
  • INA351 & INA181 appear to fit our budget requirements well
  • What shall be the impact of the relatively higher Voffset in these Current Sense amplifiers on the FSR error?
  • How do we minimize these errors with better design decisions?
• Are there any additional filter, ESD, surge, and overvoltage protection measures we should consider without compromising the signal chain characteristics?

As we are relatively new to Analog circuits, any guidance and insights from the community would be immensely helpful for me and my team.

Thank you for your time and support.

Best regards

Hi Shreeneet,

Neet said:

How can we minimize errors in the unity gain configuration with a Voffset of 1.6mV?

You have several options. One option is doing a one time calibration to check what the offset error is then use the onboard software or hardware to adjust for this. I believe Art did mention this in that previous thread.

The second option, use a different op amp with lower offset voltage and accepting the higher costs for a more precise device. 

Neet said:

Which Offset value should we consider, the typical (0,4mV) or the maximum (1.6mV) value as per the datasheet?

Both. Typical will be for what you typically expect to see, and the maximum will be designing for the worst case error. If you have a way to calibrate it the system that would greatly help minimize the effects of the offset. 

Neet said:

How can we reduce the need for external components in the CT's secondary side measurement, where a gain up to 50 may be required without exceeding the error budget of 0.2-0.4%?

• INA351 & INA181 appear to fit our budget requirements well

Using the INA351 or INA181 would help reduce the external components since they have the gain resistors integrated.

To be honest, you are reaching the point in your design where you need to decide whether you want to go with a more integrated solution or discrete solution.

Neet said:

What shall be the impact of the relatively higher Voffset in these Current Sense amplifiers on the FSR error?

A relatively higher offset means there will be relatively higher error in the signal. 

Neet said:

How do we minimize these errors with better design decisions?

Answer is the same as the first question's reply. 

Neet said:

Are there any additional filter, ESD, surge, and overvoltage protection measures we should consider without compromising the signal chain characteristics?

Op amps have internal ESD protection on both the inputs and outputs. TVS didoes on the supply rail pins can help with overvoltage protection. 

Best Regards,

Robert Clifton 

Hello Robert,

In the following circuit, the Shunt Resistor is connected to the ground of the measuring circuit. The measuring circuit is operating at 0-3.3V while the Current loop circuit is operating at 0-36V. Can you confirm if we can continue with the following suggested design or do we need to make any updates in the following design?

Robert Clifton56 said:

A relatively higher offset means there will be relatively higher error in the signal. 

I meant to ask does this error gets multiplied by the Gain in the configuration.

Robert Clifton56 said:

To be honest, you are reaching the point in your design where you need to decide whether you want to go with a more integrated solution or discrete solution.

We are looking for an integrated solution for CT-based Current measurement via Burden Resistor with gain of 5 to 50, this is clear to us. We seek guidance to help us locate better components as we have limited exposure to the TI portfolio. Once you understand our requirements, you might be able to help us with better component suggestions.

We are looking for a robust solution with a relatively relaxed error budget of up to 0.4% for both applications, looking forward for your valuable insights on which components may help us achieve a better fit between integrated solutions as well as lower costs as we have limited exposure to the TI portfolio.

Robert Clifton56 said:

You have several options

Can you share these options with us? Also for one-time calibration of the offset, we have a unipolar ADC, will this cause any calibration constraints?

Hi Shreeneet, 

Neet said:

Can you confirm if we can continue with the following suggested design or do we need to make any updates in the following design?

This is a pretty simple circuit. It looks like it should be ok based on the information you have decided. Only you can decide whether or not you should move forward with a design. 

Neet said:

Robert Clifton56 said:

A relatively higher offset means there will be relatively higher error in the signal. 

I meant to ask does this error gets multiplied by the Gain in the configuration.

I'm sorry I misunderstood. Yes the error will get multiplied by the gain. 

Neet said:

Can you share these options with us? Also for one-time calibration of the offset, we have a unipolar ADC, will this cause any calibration constraints?

I would recommend asking the ADC team this question. Which part number is this? Please create a new post asking to better understand any limitations and how to use it. 

Using the ADC is one option. Another is using a DAC. But if you don't have a DAC then I would recommend sticking with the ADC calibration method. 

Best Regards, 

Robert Clifton 

Hi Shreeneet,

Neet said:

Current Loop Circuit Details:
- Supply Voltage: 0 to 36V
- Current signal in the loop 4-20mA

Here is an example of low cost discrete 4-20mA current loop transmitter. The accuracy or errors depends on the quality of the components you used in the design. 

TLV07 Discrete 0-3.3V 4-20mA 07252023.TSC

Alternatively, you may use V/I converter, and it may work as well. Regardless what you are selecting, you will need an ultra stable LDO or bandgap reference for the discrete 4-20mA V-I converters, since temperature change and drift of digital data recorder is critical to the application. 

https://www.ti.com/lit/an/sboa327a/sboa327a.pdf?ts=1690316800099&ref_url=https%253A%252F%252Fwww.google.com%252F

Best,

Raymond