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PGA113: Output drifting away from Vref

Part Number: PGA113
Other Parts Discussed in Thread: OPA392

We are measuring faint photodiode output with a transimpedance amplifier (uses AD8605) AC coupled into a PGA (uses PGA113) followed by a low-pass filter (uses LTC1563-2).

We modified a working design by replacing the LTC6910 family PGA with the PGA113 for higher gain and SPI programming. We added Vref per Figure 72 of the datasheet (the LTC6910 had an internal half-supply reference). Unfortunately, the output drifts away from Vref. See the images of the amplifier circuit, the reference voltage circuit (called Vdc in the schematic), and a video showing behavior when the PGA gain is reduced from a value that is saturated. At first the output shrinks in half, giving a good signal, but then it drifts up to the supply voltage and saturates.

Any advice on what is going wrong? Should we add a resistor to ground somewhere to counteract the drift?

  • The output shown is before the low pass filter Slight smile

  • Hi Steve,

    It is probably an issue with the  AD device., you may want to try OPA392.. :)  But seriously, are sure the reference output from the AD8605 is stable?  100 nF is a substantial amount of capacitance for any amplifier to drive directly.  Does it go away when you remove C159?


  • Hi Mike,

    Thanks for the prompt reply and the joke! We'll check the stability/removing C159 and report back.


  • Sounds good, Steve, let us know.


  • Hi Michael 

    I'm Ariel, Steve's colleague.   

    we Removed C159 as you suggested and still see that the output is drifting up to 3.3V. see Scope screen shot.

    in addition, when we turn the laser off, we see that the DC output of the PGA drift as well. see video attached.

    the measurement is on pin 5 of the PGA.

    note: our board have 8 channels of laser detector circuits and only 2 channels are operating at a time. the Vref and Vdc circuit are powering all 8 channels.

  • Hi Ariel,

    Ok, sorry I should have caught this the first time:  you have a capacitor feeding into Ch. 1, however, there is no DC bias connection.  The amplifier input high-impedance but needs to have a DC bias path to VREF; 

    This will configure the amplifier at DC to output VREF, and AC frequencies greater than 1/(RB*CB*2*PI) to the correct gain.

    Can you add a resistor from Pin 2 to Pin 4 to set up the DC voltage on CH1 to VREF and see if that fixes it?


  • Ariel,

    A bit more detail; looks like you are trying to pass a 5 kHz signal, so I would set the resistor at something much larger than RB > 1/(68nF*5kHz*2*PI) = 468 Ohms.  A 10 kOhm resistor should be enough, unless your frequency of interest is lower than 5 kHz.


  • Mike,

    This looks like it will work. The previous part we had used referenced the inputs to the supply midpoint internally to the chip, and I guess we assumed the PGA113 did, as well. We missed Figure 81 which shows a more complicated example that references an AC coupled input to Vref but doesn't make it easy to use the VCAL outputs. Your version of Figure 69 would be a useful addition to the datasheet IMO. A 10K RB sets the 3dB point to 234 Hz, which should work for us. Ariel has the hardware and should confirm the fix tomorrow.



  • Hi Michael

    I tested your solution and it solve the problem.

    thanks for your help.


  • Hi Ariel, Steve,

    OK, great.  Let us know if anything else comes up.


  • Hi Mike

    our Vref is 1.5V.

    we see on the output that the signal is biased to 1.4V.

    do you have eny idea why?

    I try to lower the Rb from 10K to 4.7K but it didn't work.


  • Hi Ariel,

    Ok, not entirely sure at the moment.  Let me ask a few questions to dig deeper-

    1) Did you measured the voltage on the VREF pin, and verified it was indeed 1.5 V?  Basically this would rule out the buffer circuit.

    2) What do you have the gain set to in that configuration? 

    3) Does the offset voltage change when you change the gain?

    4) Can you just turn off the AC stimulus, and measure the output voltage when the AC signal is off?  


  • Hi Michael 

    1. I have measured Vref and its 1.5V.

    2. in the screen shot i send the gain was set to 20. but in general, we set the gain according to the signal strength at the input. so, the gain can change according to the signal at the input.

    3. the offset stay the same 1.4V

    4. when we stop the AC signal, we see offset of 1.45V with internal noise. when the PGA is not initialized, we see offset of 2.93V (see screen shots)

  • Hi Ariel,

    It looks like Vref is used in a couple of different ways referring to your schematic.  The VREF pin of the PGA113 is actually connected to a node called "Vdc", where the pin VCAL/CH0 is connected to a node called "Vref".  Is the bias resistor connected to the node "Vref", or the pin VREF? Any voltage differences between the pin "VREF" and the input voltage will be gained up by the PGA gain.  So, if the DC blocking cap. is connected to the "Vref" (the node) and not VREF (the pin), then the difference in the DC voltage will be gained.

    I would not have expected to see such a high offset voltage from the PGA113 itself, which is why I am suspecting the input configuration.

    Can you measure both the nodes "Vref" and "Vdc" and let me know what the voltages are?  You mentioned that "Vref" is 1.5 V, but, I'm not sure if that is the node name "Vref" or the pin VREF.

    Best Regards,

  • Hi Michael

    sorry for the confusion.

    in my circuit Vref is the refence voltage for the ADC converter and I'm using it also in the PGA for ADC calibration.

    in the PGA113 Vref pin is the half of full-scale voltage.

    so, I named the half of the full-scale voltage as Vdc.

    Vdc = 1.5V ; Vref = 3V. (verified by measurement)

    as you can see from the schematic, I connected Vdc to pin No.4 of the PGA. means pin No.4 of the PGA is connected to 1.5V.

    I added 10K resistor between pin No.2 and Pin No.4 of the PGA.


  • Ariel,

    I work with Michael and will help support your question.  In reviewing the post I see that the offset is 1.45V when no AC signal is applied and 1.4V when the AC signal is applied.  This makes me think that there is some loading happening on the voltage reference.  Can you provide more detail on the circuit that generates Vdc and Vref?  Many voltage references have limited output drive and cannot support much transient loading.  Another possibility is that the reference drive circuit is not stable.  The noise in the scope image you show is very large (about 500mVpp).  I think you are saying that you see this noise when no AC signal is applied.  The amount of noise doesn't seem reasonable as to what you would expect from a good reference.  The output noise of a good reference circuit should be in the micro-volts not 500mVpp.  Maybe I am misinterpreting the scope image.  In any case, I hope you can provide more detail on how these voltages are generated.

    Best regards,


  • Hi Art

    I tested it again and see that my Vref is something around 2.95V so Vdc will be something around 1.47V.

    this is what I get during additional measurements, and it make sense. (See attached screen shot).

    I will tune Vref and see if it solves the issue.

    but now I'm facing a new issue.

    every time we set the PGA gain, we see overshoot of few milliseconds. 

    for example:

    we inject constant signal to the PGA and rapidly set the same gain over and over again and see that every time we set the gain the output gets overshoot.

    we are sampling the signal few dozens of microseconds after we set the gain. so, it gives an error in the readings.

    see attached screenshot.

  • hi Art

    I try to change Rb (the resistor connected between input and Vdc) from 10K to 1K and i see that overshoot is lower.


  • Ariel,

    1. Just to confirm.  The issue with the Vref and Vdc is resolved.  Correct?
    2. Regarding the settling.
      1. Based on your initial schematic, it appears that your input signal is applied to CH1.  When the signal is connected into this channel, the input impedance is very high.  Assuming the reference is a low impedance voltage source, the gain setting and output signal should not impact that input signal.  I think the pictures you show of the settling issue are the PGA output.  I do not think you should see that transient feedback to the input.  The point is that I don't think changing the 10k or associated capacitor will help.  Please confirm that the input is unaffected by the gain switching, but monitoring the input signal at CH1 input of the IC with a scope.
      2. I think it is likely that the PGA feedback network is transitioned every time the gain is written to even when the same gain is written to the device.  I have not been able to confirm if this is true with any internal literature.  I will check further with other colleagues, and place the EVM on order so that I can confirm this in the lab myself.  If the gain actually did change I would expect a transient behavior while the output slews to the new value and settles.  However the specified 0.1% settling times are in the 2us time frame and not in miliseconds.  Furthermore, the data sheet does say that the "gain select time" is 0.2us.  So, even if the feedback network does transition when the same gain setting is written to it, the entire settling time should be in the microseconds not miliseconds.
      3. Related to item b.  Can you remove R48 and see if the transients are effected?  Based on the data sheet, I do not think we should see such a long transit.  Thus, I would like to disconnect everything from the output and make sure that nothing is loading the output.

    Hopefully, we can work through the circuit issues soon.  Thanks for your patience.  

    Best regards,  Art

  • Hi Art

    sorry for the late response.

    1. looks that it resolved

    2. a. yes, the pictures you show of the settling issue are the PGA output. i see that transient feedback to the input as well (see screen shot).

    c. R48 is part of LTC1563 LPF implementation. and we see the transient on the input as well. so maybe there is no point to test without R48?

  • Ariel,

    1. I have an EVM on order.  I can test the settling of the PGA in the lab.  Order placed 9/21/2023.
    2. The point of removing R48 is to isolate the PGA output from the remainder of the circuit and to check if the settling is impacted by that circuit.  You could do the same thing on the input of the PGA (e.g. cut trace to left of C65 and apply signal with test equipment to left of C65.  The point of this is to understand if the issue is because of an interaction between the PGA and the input or output circuit connected to the PGA.  According to the PGA data sheet the PGA should not take milliseconds to settle.  However, capacitive load on amplifiers or other external conditions can impact the performance of any amplifier. 
      1. For example, IC19 SA pin is connected to the PGA113 output.  Is this correct and intended?  I took a quick look at the data sheet for that device and I question this connection.  Disconnecting IC19 can help you to understand if the problem is with the PGA or IC19.
    3. When the EVM arrives, I will apply a DC and AC input and switch the gain to look at the settling.  If the device settles quickly, than we will have to look at your input and output connections to see what interaction is causing the slow settling.  
    4. Sorry for the delay on the measurement.  I think the hardware should arrive soon.

    Best regards, Art